LLVM: include/llvm/CodeGen/LiveRegUnits.h Source File (original) (raw)
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14#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
15#define LLVM_CODEGEN_LIVEREGUNITS_H
16
23#include
24
25namespace llvm {
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34
35public:
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53 if (O->isRegMask())
55 if (!O->isReg())
56 continue;
58 if (.isPhysical())
59 continue;
60 if (O->isDef()) {
61
62
63
64 if (!TRI->isConstantPhysReg(Reg))
66 } else {
67 assert(O->isUse() && "Reg operand not a def and not a use");
69 }
70 }
71 }
72
73
75 this->TRI = &TRI;
76 Units.reset();
77 Units.resize(TRI.getNumRegUnits());
78 }
79
80
81 void clear() { Units.reset(); }
82
83
84 bool empty() const { return Units.none(); }
85
86
88 for (MCRegUnit Unit : TRI->regunits(Reg))
89 Units.set(static_cast<unsigned>(Unit));
90 }
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96 auto [Unit, UnitMask] = *I;
97 if ((UnitMask & Mask).any())
98 Units.set(static_cast<unsigned>(Unit));
99 }
100 }
101
102
104 for (MCRegUnit Unit : TRI->regunits(Reg))
105 Units.reset(static_cast<unsigned>(Unit));
106 }
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118 for (MCRegUnit Unit : TRI->regunits(Reg)) {
119 if (Units.test(static_cast<unsigned>(Unit)))
120 return false;
121 }
122 return true;
123 }
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146 Units |= RegUnits;
147 }
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150 Units.reset(RegUnits);
151 }
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156
157private:
158
159
161};
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166 filter_iterator<ConstMIBundleOperands, bool (*)(const MachineOperand &)>>
169 return MOP.isRegMask() ||
170 (MOP.isReg() && !MOP.isDebug() && MOP.getReg().isPhysical());
171 };
173 static_cast<bool (*)(const MachineOperand &)>(Pred));
174}
175
176}
177
178#endif
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements the BitVector class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
Definition LiveRegUnits.h:48
LiveRegUnits(const TargetRegisterInfo &TRI)
Constructs and initialize an empty LiveRegUnits set.
Definition LiveRegUnits.h:40
bool available(MCRegister Reg) const
Returns true if no part of physical register Reg is live.
Definition LiveRegUnits.h:117
const BitVector & getBitVector() const
Return the internal bitvector representation of the set.
Definition LiveRegUnits.h:153
LLVM_ABI void addRegsInMask(const uint32_t *RegMask)
Adds register units not preserved by the regmask RegMask.
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
Definition LiveRegUnits.h:74
void addReg(MCRegister Reg)
Adds register units covered by physical register Reg.
Definition LiveRegUnits.h:87
LiveRegUnits()=default
Constructs a new empty LiveRegUnits set.
LLVM_ABI void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
LLVM_ABI void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void addUnits(const BitVector &RegUnits)
Adds all register units marked in the bitvector RegUnits.
Definition LiveRegUnits.h:145
void removeReg(MCRegister Reg)
Removes all register units covered by physical register Reg.
Definition LiveRegUnits.h:103
void addRegMasked(MCRegister Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask.
Definition LiveRegUnits.h:94
bool empty() const
Returns true if the set is empty.
Definition LiveRegUnits.h:84
LLVM_ABI void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
void removeUnits(const BitVector &RegUnits)
Removes all register units marked in the bitvector RegUnits.
Definition LiveRegUnits.h:149
LLVM_ABI void removeRegsNotPreserved(const uint32_t *RegMask)
Removes register units not preserved by the regmask RegMask.
void clear()
Clears the set.
Definition LiveRegUnits.h:81
LLVM_ABI void accumulate(const MachineInstr &MI)
Adds all register units used, defined or clobbered in MI.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
Wrapper class representing physical registers. Should be passed by value.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
Wrapper class representing virtual and physical registers.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< filter_iterator< ConstMIBundleOperands, bool(*)(const MachineOperand &)> > phys_regs_and_masks(const MachineInstr &MI)
Returns an iterator range over all physical register and mask operands for MI and bundled instruction...
Definition LiveRegUnits.h:167
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)
iterator_range(Container &&) -> iterator_range< llvm::detail::IterOfRange< Container > >
filter_iterator_impl< WrappedIteratorT, PredicateT, detail::fwd_or_bidi_tag< WrappedIteratorT > > filter_iterator
Defines filter_iterator to a suitable specialization of filter_iterator_impl, based on the underlying...