LiveVariables.cpp Source File (original) (raw)

37#include "llvm/Config/llvm-config.h"

41using namespace llvm;

54 OS << "Live variables in machine function: " << MF.getName() << '\n';

57}

62 "Live Variable Analysis", false, false)

69 AU.setPreservesAll();

71}

74 : MF(&MF), MRI(&MF.getRegInfo()), TRI(MF.getSubtarget().getRegisterInfo()) {

75 analyze(MF);

76}

79 for (size_t I = 0, E = VirtRegInfo.size(); I != E; ++I) {

81 OS << "Virtual register '%" << I << "':\n";

82 VirtRegInfo[Reg].print(OS);

83 }

84}

89 if (MI->getParent() == MBB)

90 return MI;

91 return nullptr;

92}

95 OS << " Alive in blocks: ";

97 OS << AB << ", ";

98 OS << "\n Killed by:";

99 if (Kills.empty())

100 OS << " No instructions.\n\n";

101 else {

102 for (unsigned i = 0, e = Kills.size(); i != e; ++i)

103 OS << "\n #" << i << ": " << *Kills[i];

104 OS << "\n";

105 }

106}

107

108#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

110#endif

111

112

114 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!");

115 VirtRegInfo.grow(Reg);

116 return VirtRegInfo[Reg];

117}

118

122 unsigned BBNum = MBB->getNumber();

123

124

125

126 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)

127 if (VRInfo.Kills[i]->getParent() == MBB) {

128 VRInfo.Kills.erase(VRInfo.Kills.begin()+i);

129 break;

130 }

131

132 if (MBB == DefBlock) return;

133

135 return;

136

137

139

140 assert(MBB != &MF->front() && "Can't find reaching def for virtreg");

141 WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());

142}

143

149

150 while (!WorkList.empty()) {

153 }

154}

155

158 assert(MRI->getVRegDef(Reg) && "Register use before def!");

159

160 unsigned BBNum = MBB->getNumber();

161

163

164

165 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {

166

167

168 VRInfo.Kills.back() = &MI;

169 return;

170 }

171

172#ifndef NDEBUG

174 assert(Kill->getParent() != MBB && "entry should be at end!");

175#endif

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193 if (MBB == MRI->getVRegDef(Reg)->getParent())

194 return;

195

196

197

198

200 VRInfo.Kills.push_back(&MI);

201

202

205}

206

209

211

212 VRInfo.Kills.push_back(&MI);

213}

214

215

217 unsigned LastDefDist = 0;

221 if (!Def)

222 continue;

223 unsigned Dist = DistanceMap[Def];

224 if (Dist > LastDefDist) {

225 LastDef = Def;

226 LastDefDist = Dist;

227 }

228 }

229

230 if (!LastDef)

231 return nullptr;

232

233 return LastDef;

234}

235

236

237

238

239void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {

240 MachineInstr *LastDef = PhysRegDef[Reg.id()];

241

242 if (!LastDef && !PhysRegUse[Reg.id()]) {

243

244

245

246

247

248

249

250

251 MachineInstr *LastPartialDef = FindLastPartialDef(Reg);

252

253 if (LastPartialDef) {

256 }

257 } else if (LastDef && !PhysRegUse[Reg.id()] &&

259

261 true));

262

263

266}

267

268

269

270MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {

271 MachineInstr *LastDef = PhysRegDef[Reg.id()];

272 MachineInstr *LastUse = PhysRegUse[Reg.id()];

273 if (!LastDef && !LastUse)

274 return nullptr;

275

276 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;

277 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];

278 unsigned LastPartDefDist = 0;

280 MachineInstr *Def = PhysRegDef[SubReg];

281 if (Def && Def != LastDef) {

282

283

284 unsigned Dist = DistanceMap[Def];

285 if (Dist > LastPartDefDist)

286 LastPartDefDist = Dist;

287 } else if (MachineInstr *Use = PhysRegUse[SubReg]) {

288 unsigned Dist = DistanceMap[Use];

289 if (Dist > LastRefOrPartRefDist) {

290 LastRefOrPartRefDist = Dist;

291 LastRefOrPartRef = Use;

292 }

293 }

294 }

295

296 return LastRefOrPartRef;

297}

298

299bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {

300 MachineInstr *LastDef = PhysRegDef[Reg.id()];

301 MachineInstr *LastUse = PhysRegUse[Reg.id()];

302 if (!LastDef && !LastUse)

303 return false;

304

305 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;

306 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324 MachineInstr *LastPartDef = nullptr;

325 unsigned LastPartDefDist = 0;

326 SmallSet<unsigned, 8> PartUses;

328 MachineInstr *Def = PhysRegDef[SubReg];

329 if (Def && Def != LastDef) {

330

331

332 unsigned Dist = DistanceMap[Def];

333 if (Dist > LastPartDefDist) {

334 LastPartDefDist = Dist;

335 LastPartDef = Def;

336 }

337 continue;

338 }

339 if (MachineInstr *Use = PhysRegUse[SubReg]) {

341 unsigned Dist = DistanceMap[Use];

342 if (Dist > LastRefOrPartRefDist) {

343 LastRefOrPartRefDist = Dist;

344 LastRefOrPartRef = Use;

345 }

346 }

347 }

348

349 if (!PhysRegUse[Reg.id()]) {

350

351

352

353

354 PhysRegDef[Reg.id()]->addRegisterDead(Reg, TRI, true);

357 continue;

358 bool NeedDef = true;

359 if (PhysRegDef[Reg.id()] == PhysRegDef[SubReg]) {

360 MachineOperand *MO = PhysRegDef[Reg.id()]->findRegisterDefOperand(

361 SubReg, nullptr);

362 if (MO) {

363 NeedDef = false;

365 }

366 }

367 if (NeedDef)

368 PhysRegDef[Reg.id()]->addOperand(

370 MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);

371 if (LastSubRef)

373 else {

376 PhysRegUse[SS] = LastRefOrPartRef;

377 }

379 PartUses.erase(SS);

380 }

381 } else if (LastRefOrPartRef == PhysRegDef[Reg.id()] &&

382 LastRefOrPartRef != MI) {

383 if (LastPartDef)

384

386 true, true));

387 else {

388 MachineOperand *MO =

391

392

394 if (NeedEC) {

395

396

398 if (MO)

400 }

401 }

402 } else

404 return true;

405}

406

407void LiveVariables::HandleRegMask(const MachineOperand &MO, unsigned NumRegs) {

408

409

410

411 for (unsigned Reg = 1; Reg != NumRegs; ++Reg) {

412

413 if (!PhysRegDef[Reg] && !PhysRegUse[Reg])

414 continue;

415

417 continue;

418

419

420 unsigned Super = Reg;

422 if (SR < NumRegs && (PhysRegDef[SR] || PhysRegUse[SR]) &&

424 Super = SR;

425 HandlePhysRegKill(Super, nullptr);

426 }

427}

428

429void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI,

430 SmallVectorImpl &Defs) {

431

432 SmallSet<unsigned, 32> Live;

433 if (PhysRegDef[Reg.id()] || PhysRegUse[Reg.id()]) {

435 } else {

437

438

439

440

441

442

444 continue;

445 if (PhysRegDef[SubReg] || PhysRegUse[SubReg])

447 }

448 }

449

450

451

452 HandlePhysRegKill(Reg, MI);

453

456

457 continue;

458 HandlePhysRegKill(SubReg, MI);

459 }

460

461 if (MI)

463}

464

465void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,

466 SmallVectorImpl &Defs) {

467 while (!Defs.empty()) {

471 PhysRegUse[SubReg] = nullptr;

472 }

473 }

474}

475

476void LiveVariables::runOnInstr(MachineInstr &MI,

477 SmallVectorImpl &Defs,

478 unsigned NumRegs) {

479 assert(.isDebugOrPseudoInstr());

480

481 unsigned NumOperandsToProcess = MI.getNumOperands();

482

483

484

485 if (MI.isPHI())

486 NumOperandsToProcess = 1;

487

488

492 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {

493 MachineOperand &MO = MI.getOperand(i);

496 continue;

497 }

499 continue;

501 if (MO.isUse()) {

502 if (!(MOReg.isPhysical() && MRI->isReserved(MOReg)))

506 } else {

508

509

510 if (MOReg.isPhysical() && !MRI->isReserved(MOReg))

513 }

514 }

515

516 MachineBasicBlock *MBB = MI.getParent();

517

518 for (Register MOReg : UseRegs) {

521 else if (!MRI->isReserved(MOReg))

522 HandlePhysRegUse(MOReg, MI);

523 }

524

525

526 for (unsigned Mask : RegMasks)

527 HandleRegMask(MI.getOperand(Mask), NumRegs);

528

529

530 for (Register MOReg : DefRegs) {

533 else if (!MRI->isReserved(MOReg))

534 HandlePhysRegDef(MOReg, &MI, Defs);

535 }

536 UpdatePhysRegDefs(MI, Defs);

537}

538

539void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {

540

542 for (const auto &LI : MBB->liveins()) {

543 assert(LI.PhysReg.isPhysical() &&

544 "Cannot have a live-in virtual register!");

545 HandlePhysRegDef(LI.PhysReg, nullptr, Defs);

546 }

547

548

549 DistanceMap.clear();

550 unsigned Dist = 0;

551 for (MachineInstr &MI : *MBB) {

552 if (MI.isDebugOrPseudoInstr())

553 continue;

554 DistanceMap.insert(std::make_pair(&MI, Dist++));

555

556 runOnInstr(MI, Defs, NumRegs);

557 }

558

559

560

561

562

564 SmallVectorImpl &VarInfoVec = PHIVarInfo[MBB->getNumber()];

565

567

570 }

571

572

573

574 SmallSet<unsigned, 4> LiveOuts;

575 for (const MachineBasicBlock *SuccMBB : MBB->successors()) {

576 if (SuccMBB->isEHPad())

577 continue;

578 for (const auto &LI : SuccMBB->liveins()) {

579 if (!TRI->isInAllocatableClass(LI.PhysReg))

580

581 LiveOuts.insert(LI.PhysReg);

582 }

583 }

584

585

586

587 for (unsigned i = 0; i != NumRegs; ++i)

588 if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))

589 HandlePhysRegDef(i, nullptr, Defs);

590}

591

592void LiveVariables::analyze(MachineFunction &mf) {

593 MF = &mf;

595 TRI = MF->getSubtarget().getRegisterInfo();

596

597 const unsigned NumRegs = TRI->getNumSupportedRegs(mf);

598 PhysRegDef.assign(NumRegs, nullptr);

599 PhysRegUse.assign(NumRegs, nullptr);

600 PHIVarInfo.resize(MF->getNumBlockIDs());

601

602

603

604

605 if (!MRI->isSSA())

607

608 analyzePHINodes(mf);

609

610

611

612

613

614 MachineBasicBlock *Entry = &MF->front();

615 df_iterator_default_set<MachineBasicBlock*,16> Visited;

616

618 runOnBlock(MBB, NumRegs);

619

620 PhysRegDef.assign(NumRegs, nullptr);

621 PhysRegUse.assign(NumRegs, nullptr);

622 }

623

624

625

626 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {

628 for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)

629 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))

630 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);

631 else

632 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);

633 }

634

635

636

637

638#ifndef NDEBUG

639 for (const MachineBasicBlock &MBB : *MF)

640 assert(Visited.contains(&MBB) && "unreachable basic block found");

641#endif

642

643 PhysRegDef.clear();

644 PhysRegUse.clear();

645 PHIVarInfo.clear();

646}

647

649 assert(Reg.isVirtual());

650

652 VI.AliveBlocks.clear();

653 VI.Kills.clear();

654

657

658

659

660

661

664 unsigned NumRealUses = 0;

665 for (auto &UseMO : MRI->use_nodbg_operands(Reg)) {

666 UseMO.setIsKill(false);

667 if (!UseMO.readsReg())

668 continue;

669 ++NumRealUses;

673 if (UseMI.isPHI()) {

674

675

676 unsigned Idx = UseMO.getOperandNo();

677 LiveToEndBlocks.push_back(UseMI.getOperand(Idx + 1).getMBB());

678 } else if (&UseBB == &DefBB) {

679

680 } else {

681

683 }

684 }

685

686

687 if (NumRealUses == 0) {

688 VI.Kills.push_back(&DefMI);

689 DefMI.addRegisterDead(Reg, nullptr);

690 return;

691 }

692 DefMI.clearRegisterDeads(Reg);

693

694

695 bool LiveToEndOfDefBB = false;

696 while (!LiveToEndBlocks.empty()) {

698 if (&BB == &DefBB) {

699 LiveToEndOfDefBB = true;

700 continue;

701 }

702 if (VI.AliveBlocks.test(BB.getNumber()))

703 continue;

704 VI.AliveBlocks.set(BB.getNumber());

706 }

707

708

709

710

711 for (unsigned UseBBNum : UseBlocks) {

712 if (VI.AliveBlocks.test(UseBBNum))

713 continue;

715 if (&UseBB == &DefBB && LiveToEndOfDefBB)

716 continue;

717 for (auto &MI : reverse(UseBB)) {

718 if (MI.isDebugOrPseudoInstr())

719 continue;

720 if (MI.isPHI())

721 break;

722 if (MI.readsVirtualRegister(Reg)) {

723 assert(.killsRegister(Reg, nullptr));

724 MI.addRegisterKilled(Reg, nullptr);

725 VI.Kills.push_back(&MI);

726 break;

727 }

728 }

729 }

730}

731

732

733

739

740

741

747 if (Reg.isVirtual()) {

749 assert(removed && "kill not in register's VarInfo?");

750 (void)removed;

751 }

752 }

753 }

754}

755

756

757

758

759

760void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {

761 for (const auto &MBB : Fn)

762 for (const auto &BBI : MBB) {

763 if (!BBI.isPHI())

764 break;

765 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)

766 if (BBI.getOperand(i).readsReg())

767 PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]

768 .push_back(BBI.getOperand(i).getReg());

769 }

770}

771

774 unsigned Num = MBB.getNumber();

775

776

778 return true;

779

780

781 const MachineInstr *Def = MRI.getVRegDef(Reg);

782 if (Def && Def->getParent() == &MBB)

783 return false;

784

785

787}

788

791

794 Kills.insert(MI->getParent());

795

796

797

799

800 unsigned SuccIdx = SuccMBB->getNumber();

801 if (VI.AliveBlocks.test(SuccIdx))

802 return true;

803

804 if (Kills.count(SuccMBB))

805 return true;

806 }

807

808 return false;

809}

810

811

812

813

817 const unsigned NumNew = BB->getNumber();

818

820

822 for (; BBI != BBE && BBI->isPHI(); ++BBI) {

823

824 Defs.insert(BBI->getOperand(0).getReg());

825

826

827 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)

828 if (BBI->getOperand(i+1).getMBB() == BB)

830 }

831

832

833 for (; BBI != BBE; ++BBI) {

835 if (Op.isReg() && Op.getReg().isVirtual()) {

836 if (Op.isDef())

838 else if (Op.isKill())

840 }

841 }

842 }

843

844

845 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

847

848

849 if (Defs.count(Reg))

850 continue;

851

852

853

855 if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))

856 VI.AliveBlocks.set(NumNew);

857 }

858}

859

860

861

862

863

868 const unsigned NumNew = BB->getNumber();

869

871 for (unsigned R : BV) {

874 VI.AliveBlocks.set(NumNew);

875 }

876

878 BBE = SuccBB->end();

879 BBI != BBE && BBI->isPHI(); ++BBI) {

880 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)

881 if (BBI->getOperand(i + 1).getMBB() == BB &&

882 BBI->getOperand(i).readsReg())

883 getVarInfo(BBI->getOperand(i).getReg())

885 }

886}

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

This file defines the DenseSet and SmallDenseSet classes.

This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.

Promote Memory to Register

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file defines the SmallPtrSet class.

This file defines the SmallSet class.

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

Implements a dense probed hash-table based set.

LLVM_ABI Result run(MachineFunction &MF, MachineFunctionAnalysisManager &)

Definition LiveVariables.cpp:46

LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition LiveVariables.cpp:52

LiveVariablesWrapperPass()

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...

Definition LiveVariables.cpp:67

LLVM_ABI void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)

replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.

Definition LiveVariables.cpp:734

LLVM_ABI void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *BB)

Definition LiveVariables.cpp:144

LLVM_ABI void removeVirtualRegistersKilled(MachineInstr &MI)

removeVirtualRegistersKilled - Remove all killed info for the specified instruction.

Definition LiveVariables.cpp:742

LLVM_ABI bool isLiveOut(Register Reg, const MachineBasicBlock &MBB)

isLiveOut - Determine if Reg is live out from MBB, when not considering PHI nodes.

Definition LiveVariables.cpp:789

LLVM_ABI void HandleVirtRegDef(Register reg, MachineInstr &MI)

Definition LiveVariables.cpp:207

LLVM_ABI void print(raw_ostream &OS) const

Definition LiveVariables.cpp:78

LLVM_ABI void recomputeForSingleDefVirtReg(Register Reg)

Recompute liveness from scratch for a virtual register Reg that is known to have a single def that do...

Definition LiveVariables.cpp:648

LLVM_ABI void HandleVirtRegUse(Register reg, MachineBasicBlock *MBB, MachineInstr &MI)

Definition LiveVariables.cpp:156

LLVM_ABI VarInfo & getVarInfo(Register Reg)

getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.

Definition LiveVariables.cpp:113

LLVM_ABI void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)

addNewBlock - Add a new basic block BB between DomBB and SuccBB.

Definition LiveVariables.cpp:814

iterator_range< livein_iterator > liveins() const

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

pred_iterator pred_begin()

iterator_range< succ_iterator > successors()

MachineInstrBundleIterator< MachineInstr > iterator

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Representation of each machine instruction.

LLVM_ABI void addOperand(MachineFunction &MF, const MachineOperand &Op)

Add the specified operand to the instruction.

LLVM_ABI bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI kills a register.

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

LLVM_ABI bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI defined a register without a use.

MachineOperand class - Representation of each machine instruction operand.

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

void setIsDead(bool Val=true)

void setIsKill(bool Val=true)

void setIsEarlyClobber(bool Val=true)

bool isEarlyClobber() const

getReg - Returns the register number.

static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr unsigned id() const

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

size_type count(ConstPtrType Ptr) const

count - Return 1 if the specified pointer is in the set, 0 otherwise.

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

bool contains(ConstPtrType Ptr) const

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

size_type count(const T &V) const

count - Return 1 if the element is in the set, 0 otherwise.

void insert_range(Range &&R)

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void append(ItTy in_start, ItTy in_end)

Add the specified range to the end of the SmallVector.

iterator insert(iterator I, T &&Elt)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

bool test(unsigned Idx) const

std::pair< iterator, bool > insert(const ValueT &V)

size_type count(const_arg_type_t< ValueT > V) const

Return 1 if the specified key is in the set, 0 otherwise.

This class implements an extremely fast bulk output stream that can only output to a stream.

NodeAddr< DefNode * > Def

NodeAddr< UseNode * > Use

This is an optimization pass for GlobalISel generic memory operations.

iterator_range< df_ext_iterator< T, SetTy > > depth_first_ext(const T &G, SetTy &S)

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

auto reverse(ContainerTy &&C)

LLVM_ABI char & UnreachableMachineBlockElimID

UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

void replace(R &&Range, const T &OldValue, const T &NewValue)

Provide wrappers to std::replace which take ranges instead of having to pass begin/end explicitly.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

LLVM_ABI char & LiveVariablesID

LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...

Definition LiveVariables.cpp:60

LLVM_ABI void reportFatalUsageError(Error Err)

Report a fatal error that does not indicate a bug in LLVM.

A special type used by analysis passes to provide an address that identifies that particular analysis...

VarInfo - This represents the regions where a virtual register is live in the program.

bool removeKill(MachineInstr &MI)

removeKill - Delete a kill corresponding to the specified machine instruction.

LLVM_ABI void dump() const

Definition LiveVariables.cpp:109

std::vector< MachineInstr * > Kills

Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...

SparseBitVector AliveBlocks

AliveBlocks - Set of blocks in which this value is alive completely through.

LLVM_ABI MachineInstr * findKill(const MachineBasicBlock *MBB) const

findKill - Find a kill instruction in MBB. Return NULL if none is found.

Definition LiveVariables.cpp:87

LLVM_ABI void print(raw_ostream &OS) const

Definition LiveVariables.cpp:94

LLVM_ABI bool isLiveIn(const MachineBasicBlock &MBB, Register Reg, MachineRegisterInfo &MRI)

isLiveIn - Is Reg live in to MBB?

Definition LiveVariables.cpp:772