LiveVariables.cpp Source File (original) (raw)

37#include "llvm/Config/llvm-config.h"

41#include

42using namespace llvm;

50}

55 OS << "Live variables in machine function: " << MF.getName() << '\n';

58}

63 "Live Variable Analysis", false, false)

70 AU.setPreservesAll();

72}

75 : MF(&MF), MRI(&MF.getRegInfo()), TRI(MF.getSubtarget().getRegisterInfo()) {

76 analyze(MF);

77}

80 for (size_t I = 0, E = VirtRegInfo.size(); I != E; ++I) {

82 OS << "Virtual register '%" << I << "':\n";

84 }

85}

90 if (MI->getParent() == MBB)

91 return MI;

92 return nullptr;

93}

96 OS << " Alive in blocks: ";

97 for (unsigned AB : AliveBlocks)

98 OS << AB << ", ";

99 OS << "\n Killed by:";

100 if (Kills.empty())

101 OS << " No instructions.\n\n";

102 else {

103 for (unsigned i = 0, e = Kills.size(); i != e; ++i)

104 OS << "\n #" << i << ": " << *Kills[i];

105 OS << "\n";

106 }

107}

108

109#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

111#endif

112

113

115 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!");

118}

119

124

125

126

127 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)

128 if (VRInfo.Kills[i]->getParent() == MBB) {

129 VRInfo.Kills.erase(VRInfo.Kills.begin()+i);

130 break;

131 }

132

133 if (MBB == DefBlock) return;

134

136 return;

137

138

140

141 assert(MBB != &MF->front() && "Can't find reaching def for virtreg");

143}

144

150

151 while (!WorkList.empty()) {

154 }

155}

156

160

162

164

165

166 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {

167

168

169 VRInfo.Kills.back() = &MI;

170 return;

171 }

172

173#ifndef NDEBUG

175 assert(Kill->getParent() != MBB && "entry should be at end!");

176#endif

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

195 return;

196

197

198

199

201 VRInfo.Kills.push_back(&MI);

202

203

206}

207

210

212

213 VRInfo.Kills.push_back(&MI);

214}

215

216

217

219LiveVariables::FindLastPartialDef(Register Reg,

222 unsigned LastDefDist = 0;

226 if (!Def)

227 continue;

228 unsigned Dist = DistanceMap[Def];

229 if (Dist > LastDefDist) {

231 LastDef = Def;

232 LastDefDist = Dist;

233 }

234 }

235

236 if (!LastDef)

237 return nullptr;

238

239 PartDefRegs.insert(LastDefReg);

241 if (MO.getReg() == 0)

242 continue;

243 Register DefReg = MO.getReg();

247 }

248 }

249 return LastDef;

250}

251

252

253

254

257

258 if (!LastDef && !PhysRegUse[Reg]) {

259

260

261

262

263

264

265

266

268 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);

269

270 if (LastPartialDef) {

272 true));

273 PhysRegDef[Reg] = LastPartialDef;

277 continue;

279 continue;

280

281

283 false,

284 true));

285 PhysRegDef[SubReg] = LastPartialDef;

287 Processed.insert(SS);

288 }

289 }

290 } else if (LastDef && !PhysRegUse[Reg] &&

292

294 true));

295

296

299}

300

301

302

306 if (!LastDef && !LastUse)

307 return nullptr;

308

309 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;

310 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];

311 unsigned LastPartDefDist = 0;

314 if (Def && Def != LastDef) {

315

316

317 unsigned Dist = DistanceMap[Def];

318 if (Dist > LastPartDefDist)

319 LastPartDefDist = Dist;

321 unsigned Dist = DistanceMap[Use];

322 if (Dist > LastRefOrPartRefDist) {

323 LastRefOrPartRefDist = Dist;

324 LastRefOrPartRef = Use;

325 }

326 }

327 }

328

329 return LastRefOrPartRef;

330}

331

335 if (!LastDef && !LastUse)

336 return false;

337

338 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;

339 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

358 unsigned LastPartDefDist = 0;

362 if (Def && Def != LastDef) {

363

364

365 unsigned Dist = DistanceMap[Def];

366 if (Dist > LastPartDefDist) {

367 LastPartDefDist = Dist;

368 LastPartDef = Def;

369 }

370 continue;

371 }

375 unsigned Dist = DistanceMap[Use];

376 if (Dist > LastRefOrPartRefDist) {

377 LastRefOrPartRefDist = Dist;

378 LastRefOrPartRef = Use;

379 }

380 }

381 }

382

383 if (!PhysRegUse[Reg]) {

384

385

386

387

388 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);

391 continue;

392 bool NeedDef = true;

393 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {

395 PhysRegDef[Reg]->findRegisterDefOperand(SubReg, nullptr);

396 if (MO) {

397 NeedDef = false;

399 }

400 }

401 if (NeedDef)

403 true, true));

405 if (LastSubRef)

407 else {

410 PhysRegUse[SS] = LastRefOrPartRef;

411 }

413 PartUses.erase(SS);

414 }

415 } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {

416 if (LastPartDef)

417

419 true, true));

420 else {

424

425

427 if (NeedEC) {

428

429

431 if (MO)

433 }

434 }

435 } else

437 return true;

438}

439

440void LiveVariables::HandleRegMask(const MachineOperand &MO, unsigned NumRegs) {

441

442

443

444 for (unsigned Reg = 1; Reg != NumRegs; ++Reg) {

445

446 if (!PhysRegDef[Reg] && !PhysRegUse[Reg])

447 continue;

448

450 continue;

451

452

453 unsigned Super = Reg;

455 if (SR < NumRegs && (PhysRegDef[SR] || PhysRegUse[SR]) &&

457 Super = SR;

458 HandlePhysRegKill(Super, nullptr);

459 }

460}

461

464

466 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {

469 } else {

471

472

473

474

475

476

478 continue;

479 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {

481 Live.insert(SS);

482 }

483 }

484 }

485

486

487

488 HandlePhysRegKill(Reg, MI);

489

492

493 continue;

494 HandlePhysRegKill(SubReg, MI);

495 }

496

497 if (MI)

498 Defs.push_back(Reg);

499}

500

501void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,

503 while (!Defs.empty()) {

507 PhysRegUse[SubReg] = nullptr;

508 }

509 }

510}

511

514 unsigned NumRegs) {

515 assert(.isDebugOrPseudoInstr());

516

517 unsigned NumOperandsToProcess = MI.getNumOperands();

518

519

520

521 if (MI.isPHI())

522 NumOperandsToProcess = 1;

523

524

528 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {

532 continue;

533 }

535 continue;

537 if (MO.isUse()) {

542 } else {

544

545

549 }

550 }

551

553

554 for (Register MOReg : UseRegs) {

558 HandlePhysRegUse(MOReg, MI);

559 }

560

561

562 for (unsigned Mask : RegMasks)

563 HandleRegMask(MI.getOperand(Mask), NumRegs);

564

565

566 for (Register MOReg : DefRegs) {

570 HandlePhysRegDef(MOReg, &MI, Defs);

571 }

572 UpdatePhysRegDefs(MI, Defs);

573}

574

576

578 for (const auto &LI : MBB->liveins()) {

580 "Cannot have a live-in virtual register!");

581 HandlePhysRegDef(LI.PhysReg, nullptr, Defs);

582 }

583

584

585 DistanceMap.clear();

586 unsigned Dist = 0;

588 if (MI.isDebugOrPseudoInstr())

589 continue;

590 DistanceMap.insert(std::make_pair(&MI, Dist++));

591

592 runOnInstr(MI, Defs, NumRegs);

593 }

594

595

596

597

598

601

602 for (unsigned I : VarInfoVec)

603

606 }

607

608

609

612 if (SuccMBB->isEHPad())

613 continue;

614 for (const auto &LI : SuccMBB->liveins()) {

616

617 LiveOuts.insert(LI.PhysReg);

618 }

619 }

620

621

622

623 for (unsigned i = 0; i != NumRegs; ++i)

624 if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))

625 HandlePhysRegDef(i, nullptr, Defs);

626}

627

629 MF = &mf;

632

634 PhysRegDef.assign(NumRegs, nullptr);

635 PhysRegUse.assign(NumRegs, nullptr);

637

638

639

640

641 if (!MRI->isSSA())

643

644 analyzePHINodes(mf);

645

646

647

648

649

652

654 runOnBlock(MBB, NumRegs);

655

656 PhysRegDef.assign(NumRegs, nullptr);

657 PhysRegUse.assign(NumRegs, nullptr);

658 }

659

660

661

662 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {

664 for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)

667 else

669 }

670

671

672

673

674#ifndef NDEBUG

676 assert(Visited.contains(&MBB) && "unreachable basic block found");

677#endif

678

679 PhysRegDef.clear();

680 PhysRegUse.clear();

681 PHIVarInfo.clear();

682}

683

685 assert(Reg.isVirtual());

686

688 VI.AliveBlocks.clear();

689 VI.Kills.clear();

690

693

694

695

696

697

700 unsigned NumRealUses = 0;

702 UseMO.setIsKill(false);

703 if (!UseMO.readsReg())

704 continue;

705 ++NumRealUses;

709 if (UseMI.isPHI()) {

710

711

712 unsigned Idx = UseMO.getOperandNo();

714 } else if (&UseBB == &DefBB) {

715

716 } else {

717

719 }

720 }

721

722

723 if (NumRealUses == 0) {

724 VI.Kills.push_back(&DefMI);

725 DefMI.addRegisterDead(Reg, nullptr);

726 return;

727 }

728 DefMI.clearRegisterDeads(Reg);

729

730

731 bool LiveToEndOfDefBB = false;

732 while (!LiveToEndBlocks.empty()) {

734 if (&BB == &DefBB) {

735 LiveToEndOfDefBB = true;

736 continue;

737 }

738 if (VI.AliveBlocks.test(BB.getNumber()))

739 continue;

740 VI.AliveBlocks.set(BB.getNumber());

742 }

743

744

745

746

747 for (unsigned UseBBNum : UseBlocks) {

748 if (VI.AliveBlocks.test(UseBBNum))

749 continue;

751 if (&UseBB == &DefBB && LiveToEndOfDefBB)

752 continue;

753 for (auto &MI : reverse(UseBB)) {

754 if (MI.isDebugOrPseudoInstr())

755 continue;

756 if (MI.isPHI())

757 break;

758 if (MI.readsVirtualRegister(Reg)) {

759 assert(.killsRegister(Reg, nullptr));

760 MI.addRegisterKilled(Reg, nullptr);

761 VI.Kills.push_back(&MI);

762 break;

763 }

764 }

765 }

766}

767

768

769

773 std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI);

774}

775

776

777

783 if (Reg.isVirtual()) {

785 assert(removed && "kill not in register's VarInfo?");

786 (void)removed;

787 }

788 }

789 }

790}

791

792

793

794

795

796void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {

797 for (const auto &MBB : Fn)

798 for (const auto &BBI : MBB) {

799 if (!BBI.isPHI())

800 break;

801 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)

802 if (BBI.getOperand(i).readsReg())

803 PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]

804 .push_back(BBI.getOperand(i).getReg());

805 }

806}

807

811

812

813 if (AliveBlocks.test(Num))

814 return true;

815

816

818 if (Def && Def->getParent() == &MBB)

819 return false;

820

821

822 return findKill(&MBB);

823}

824

827

830 Kills.insert(MI->getParent());

831

832

833

835

836 unsigned SuccIdx = SuccMBB->getNumber();

837 if (VI.AliveBlocks.test(SuccIdx))

838 return true;

839

840 if (Kills.count(SuccMBB))

841 return true;

842 }

843

844 return false;

845}

846

847

848

849

853 const unsigned NumNew = BB->getNumber();

854

856

858 for (; BBI != BBE && BBI->isPHI(); ++BBI) {

859

860 Defs.insert(BBI->getOperand(0).getReg());

861

862

863 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)

864 if (BBI->getOperand(i+1).getMBB() == BB)

866 }

867

868

869 for (; BBI != BBE; ++BBI) {

871 if (Op.isReg() && Op.getReg().isVirtual()) {

872 if (Op.isDef())

874 else if (Op.isKill())

876 }

877 }

878 }

879

880

881 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {

883

884

885 if (Defs.count(Reg))

886 continue;

887

888

889

891 if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))

892 VI.AliveBlocks.set(NumNew);

893 }

894}

895

896

897

898

899

904 const unsigned NumNew = BB->getNumber();

905

907 for (unsigned R : BV) {

910 VI.AliveBlocks.set(NumNew);

911 }

912

914 BBE = SuccBB->end();

915 BBI != BBE && BBI->isPHI(); ++BBI) {

916 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)

917 if (BBI->getOperand(i + 1).getMBB() == BB &&

918 BBI->getOperand(i).readsReg())

919 getVarInfo(BBI->getOperand(i).getReg())

921 }

922}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

block Block Frequency Analysis

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is Live

This file defines the DenseSet and SmallDenseSet classes.

This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallPtrSet class.

This file defines the SmallSet class.

A container for analyses that lazily runs them and caches their results.

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

This class represents an Operation in the Expression.

Implements a dense probed hash-table based set.

Result run(MachineFunction &MF, MachineFunctionAnalysisManager &)

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)

replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.

void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *BB)

void removeVirtualRegistersKilled(MachineInstr &MI)

removeVirtualRegistersKilled - Remove all killed info for the specified instruction.

bool isLiveOut(Register Reg, const MachineBasicBlock &MBB)

isLiveOut - Determine if Reg is live out from MBB, when not considering PHI nodes.

void HandleVirtRegDef(Register reg, MachineInstr &MI)

void print(raw_ostream &OS) const

void recomputeForSingleDefVirtReg(Register Reg)

Recompute liveness from scratch for a virtual register Reg that is known to have a single def that do...

void HandleVirtRegUse(Register reg, MachineBasicBlock *MBB, MachineInstr &MI)

VarInfo & getVarInfo(Register Reg)

getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.

void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)

addNewBlock - Add a new basic block BB between DomBB and SuccBB.

iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const

Return an iterator range over all super-registers of Reg, excluding Reg.

iterator_range< MCSubRegIterator > subregs_inclusive(MCRegister Reg) const

Return an iterator range over all sub-registers of Reg, including Reg.

bool isSubRegister(MCRegister RegA, MCRegister RegB) const

Returns true if RegB is a sub-register of RegA.

iterator_range< MCSubRegIterator > subregs(MCRegister Reg) const

Return an iterator range over all sub-registers of Reg, excluding Reg.

iterator_range< livein_iterator > liveins() const

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

pred_reverse_iterator pred_rbegin()

pred_reverse_iterator pred_rend()

pred_iterator pred_begin()

iterator_range< succ_iterator > successors()

iterator_range< pred_iterator > predecessors()

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

unsigned getNumBlockIDs() const

getNumBlockIDs - Return the number of MBB ID's allocated.

const MachineBasicBlock & front() const

Representation of each machine instruction.

const MachineBasicBlock * getParent() const

void addOperand(MachineFunction &MF, const MachineOperand &Op)

Add the specified operand to the instruction.

bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI kills a register.

iterator_range< filtered_mop_iterator > all_defs()

Returns an iterator range over all operands that are (explicit or implicit) register defs.

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

We have determined MI defined a register without a use.

MachineOperand class - Representation of each machine instruction operand.

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

void setIsDead(bool Val=true)

void setIsKill(bool Val=true)

void setIsEarlyClobber(bool Val=true)

bool isEarlyClobber() const

getReg - Returns the register number.

static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const

bool isReserved(MCRegister PhysReg) const

isReserved - Returns true when PhysReg is a reserved register.

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

MachineInstr * getUniqueVRegDef(Register Reg) const

getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

static constexpr bool isPhysicalRegister(unsigned Reg)

Return true if the specified register number is in the physical register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

size_type count(ConstPtrType Ptr) const

count - Return 1 if the specified pointer is in the set, 0 otherwise.

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

bool contains(ConstPtrType Ptr) const

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

size_type count(const T &V) const

count - Return 1 if the element is in the set, 0 otherwise.

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void append(ItTy in_start, ItTy in_end)

Add the specified range to the end of the SmallVector.

iterator insert(iterator I, T &&Elt)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

bool test(unsigned Idx) const

virtual unsigned getNumSupportedRegs(const MachineFunction &) const

Return the number of registers for the function. (may overestimate)

bool isInAllocatableClass(MCRegister RegNo) const

Return true if the register is in the allocation of any register class.

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

A Use represents the edge between a Value definition and its users.

std::pair< iterator, bool > insert(const ValueT &V)

size_type count(const_arg_type_t< ValueT > V) const

Return 1 if the specified key is in the set, 0 otherwise.

This class implements an extremely fast bulk output stream that can only output to a stream.

Reg

All possible values of the reg field in the ModR/M byte.

NodeAddr< DefNode * > Def

This is an optimization pass for GlobalISel generic memory operations.

iterator_range< df_ext_iterator< T, SetTy > > depth_first_ext(const T &G, SetTy &S)

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)

auto reverse(ContainerTy &&C)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

char & LiveVariablesID

LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...

char & UnreachableMachineBlockElimID

UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.

A special type used by analysis passes to provide an address that identifies that particular analysis...

VarInfo - This represents the regions where a virtual register is live in the program.

bool removeKill(MachineInstr &MI)

removeKill - Delete a kill corresponding to the specified machine instruction.

std::vector< MachineInstr * > Kills

Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...

SparseBitVector AliveBlocks

AliveBlocks - Set of blocks in which this value is alive completely through.

MachineInstr * findKill(const MachineBasicBlock *MBB) const

findKill - Find a kill instruction in MBB. Return NULL if none is found.

void print(raw_ostream &OS) const

bool isLiveIn(const MachineBasicBlock &MBB, Register Reg, MachineRegisterInfo &MRI)

isLiveIn - Is Reg live in to MBB? This means that Reg is live through MBB, or it is killed in MBB.

VirtRegInfo - Information about a virtual register used by a set of operands.