LoongArchInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H

14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H

19#define GET_INSTRINFO_HEADER

20#include "LoongArchGenInstrInfo.inc"

22namespace llvm {

24class LoongArchSubtarget;

29public:

38 bool KillSrc, bool RenamableDest = false,

39 bool RenamableSrc = false) const override;

64 bool AllowModify) const override;

67 int64_t BrOffset) const override;

77 int *BytesRemoved = nullptr) const override;

82 int *BytesAdded = nullptr) const override;

87 int64_t BrOffset, RegScavenger *RS) const override;

89 bool

92 std::pair<unsigned, unsigned>

100

106

107protected:

109};

110

112

113

115

116

127}

128

129}

130#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override

const LoongArchSubtarget & STI

Definition LoongArchInstrInfo.h:108

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

bool isSafeToMove(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

const LoongArchRegisterInfo & getRegisterInfo() const

Definition LoongArchInstrInfo.h:32

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

bool isAsCheapAsAMove(const MachineInstr &MI) const override

MCInst getNop() const override

LoongArchInstrInfo(const LoongArchSubtarget &STI)

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override

void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override

bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override

MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const override

Instances of this class represent a single low-level machine instruction.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

static constexpr unsigned FClassMaskSignalingNaN