LoongArchMCTargetDesc.cpp Source File (original) (raw)

29#include

31#define GET_INSTRINFO_MC_DESC

32#define ENABLE_INSTR_PREDICATE_VERIFIER

33#include "LoongArchGenInstrInfo.inc"

35#define GET_REGINFO_MC_DESC

36#include "LoongArchGenRegisterInfo.inc"

38#define GET_SUBTARGETINFO_MC_DESC

39#include "LoongArchGenSubtargetInfo.inc"

41using namespace llvm;

45 InitLoongArchMCRegisterInfo(X, LoongArch::R1);

46 return X;

47}

51 InitLoongArchMCInstrInfo(X);

52 return X;

53}

57 if (CPU.empty() || CPU == "generic")

58 CPU = TT.isArch64Bit() ? "generic-la64" : "generic-la32";

59 return createLoongArchMCSubtargetInfoImpl(TT, CPU, CPU, FS);

60}

68 unsigned SP = MRI.getDwarfRegNum(LoongArch::R3, true);

72 return MAI;

73}

76 unsigned SyntaxVariant,

81}

96namespace {

99 int64_t GPRState[31] = {};

100 std::bitset<31> GPRValidMask;

101

102 static bool isGPR(MCRegister Reg) {

103 return Reg >= LoongArch::R0 && Reg <= LoongArch::R31;

104 }

105

106 static unsigned getRegIndex(MCRegister Reg) {

107 assert(isGPR(Reg) && Reg != LoongArch::R0 && "Invalid GPR reg");

108 return Reg - LoongArch::R1;

109 }

110

111 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {

112 if (Reg == LoongArch::R0)

113 return;

114

115 auto Index = getRegIndex(Reg);

116

119 GPRValidMask.set(Index);

120 } else {

121 GPRValidMask.reset(Index);

122 }

123 }

124

125 std::optional<int64_t> getGPRState(MCRegister Reg) const {

126 if (Reg == LoongArch::R0)

127 return 0;

128

129 auto Index = getRegIndex(Reg);

130

131 if (GPRValidMask.test(Index))

132 return GPRState[Index];

133 return std::nullopt;

134 }

135

136public:

137 explicit LoongArchMCInstrAnalysis(const MCInstrInfo *Info)

138 : MCInstrAnalysis(Info) {}

139

140 void resetState() override { GPRValidMask.reset(); }

141

142 void updateState(const MCInst &Inst, uint64_t Addr) override {

143

144

145

146

147

148 if (isTerminator(Inst) || isCall(Inst)) {

149 resetState();

150 return;

151 }

152

154 default: {

155

156

157 auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();

158 for (unsigned I = 0; I < NumDefs; ++I) {

160 if (isGPR(DefReg))

161 setGPRState(DefReg, std::nullopt);

162 }

163 break;

164 }

165 case LoongArch::PCADDU18I:

166 setGPRState(

170 break;

171 }

172 }

173

174 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,

175 uint64_t &Target) const override {

177 if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||

178 Inst.getOpcode() == LoongArch::BL) {

180 return true;

181 }

182

183 if (Inst.getOpcode() == LoongArch::JIRL) {

184 if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {

186 return true;

187 }

188 return false;

189 }

190

191 return false;

192 }

193

194 bool isTerminator(const MCInst &Inst) const override {

196 return true;

197

199 default:

200 return false;

201 case LoongArch::JIRL:

203 }

204 }

205

206 bool isCall(const MCInst &Inst) const override {

208 return true;

209

211 default:

212 return false;

213 case LoongArch::JIRL:

215 }

216 }

217

218 bool isReturn(const MCInst &Inst) const override {

220 return true;

221

223 default:

224 return false;

225 case LoongArch::JIRL:

228 }

229 }

230

231 bool isBranch(const MCInst &Inst) const override {

233 return true;

234

236 default:

237 return false;

238 case LoongArch::JIRL:

241 }

242 }

243

246 return true;

247

249 default:

250 return false;

251 case LoongArch::JIRL:

254 }

255 }

256

257 bool isIndirectBranch(const MCInst &Inst) const override {

259 return true;

260

262 default:

263 return false;

264 case LoongArch::JIRL:

267 }

268 }

269};

270

271}

272

274 return new LoongArchMCInstrAnalysis(Info);

275}

276

277namespace {

279 std::unique_ptr &&MAB,

280 std::unique_ptr &&MOW,

281 std::unique_ptr &&MCE) {

283 std::move(MCE));

284}

285}

286

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isUnconditionalBranch(Instruction *Term)

Analysis containing CSE Info

#define LLVM_EXTERNAL_VISIBILITY

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

static MCSubtargetInfo * createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)

Definition LoongArchMCTargetDesc.cpp:56

static MCTargetStreamer * createLoongArchObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)

Definition LoongArchMCTargetDesc.cpp:84

static MCInstPrinter * createLoongArchMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)

Definition LoongArchMCTargetDesc.cpp:75

static MCRegisterInfo * createLoongArchMCRegisterInfo(const Triple &TT)

Definition LoongArchMCTargetDesc.cpp:43

static MCTargetStreamer * createLoongArchAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)

Definition LoongArchMCTargetDesc.cpp:91

static MCAsmInfo * createLoongArchMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)

Definition LoongArchMCTargetDesc.cpp:62

static MCInstrAnalysis * createLoongArchInstrAnalysis(const MCInstrInfo *Info)

Definition LoongArchMCTargetDesc.cpp:273

static MCInstrInfo * createLoongArchMCInstrInfo()

Definition LoongArchMCTargetDesc.cpp:49

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTargetMC()

Definition LoongArchMCTargetDesc.cpp:288

static bool isBranch(unsigned Opcode)

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This class is intended to be used as a base class for asm properties and features specific to the tar...

void addInitialFrameState(const MCCFIInstruction &Inst)

static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})

.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.

Context object for machine code objects.

This is an instance of a target assembly language printer that converts an MCInst to valid target ass...

unsigned getNumOperands() const

unsigned getOpcode() const

const MCOperand & getOperand(unsigned i) const

virtual bool isCall(const MCInst &Inst) const

virtual bool isBranch(const MCInst &Inst) const

virtual bool isUnconditionalBranch(const MCInst &Inst) const

virtual bool isTerminator(const MCInst &Inst) const

virtual bool isReturn(const MCInst &Inst) const

virtual bool isIndirectBranch(const MCInst &Inst) const

Interface to description of machine instruction set.

MCRegister getReg() const

Returns the register number.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Streaming machine code generation interface.

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

Target specific streamer interface.

StringRef - Represent a constant reference to a string, i.e.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

bool isOSBinFormatELF() const

Tests whether the OS uses the ELF binary format.

formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheLoongArch64Target()

FunctionAddr VTableAddr Value

MCCodeEmitter * createLoongArchMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

MCAsmBackend * createLoongArchAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Target & getTheLoongArch32Target()

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

MCELFStreamer * createLoongArchELFStreamer(MCContext &C, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > MOW, std::unique_ptr< MCCodeEmitter > MCE)

static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)

RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.

static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)

RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.

static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)

RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.

static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)

RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.

static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)

RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.

static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)

static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)

RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.

static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)

static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)

RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.

static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)

RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.

static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)