LoongArchMergeBaseOffset.cpp Source File (original) (raw)

21#include

23using namespace llvm;

25#define DEBUG_TYPE "loongarch-merge-base-offset"

26#define LoongArch_MERGE_BASE_OFFSET_NAME "LoongArch Merge Base Offset"

28namespace {

34public:

35 static char ID;

62 }

64 void getAnalysisUsage(AnalysisUsage &AU) const override {

67 }

69 StringRef getPassName() const override {

71 }

72};

73}

75char LoongArchMergeBaseOffsetOpt::ID = 0;

100bool LoongArchMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi20,

105 if (Hi20.getOpcode() != LoongArch::PCALAU12I)

106 return false;

107

110 return false;

111

112 auto isGlobalOrCPIOrBlockAddress = [](const MachineOperand &Op) {

113 return Op.isGlobal() || Op.isCPI() || Op.isBlockAddress();

114 };

115

116 if (!isGlobalOrCPIOrBlockAddress(Hi20Op1) || Hi20Op1.getOffset() != 0)

117 return false;

118

119 Register HiDestReg = Hi20.getOperand(0).getReg();

120 if ( MRI ->hasOneUse(HiDestReg))

121 return false;

122

123 MachineInstr *UseInst = &*MRI->use_instr_begin(HiDestReg);

124 if (UseInst->getOpcode() != LoongArch::ADD_D) {

125 Lo12 = UseInst;

126 if ((ST->is64Bit() && Lo12->getOpcode() != LoongArch::ADDI_D) ||

127 (!ST->is64Bit() && Lo12->getOpcode() != LoongArch::ADDI_W))

128 return false;

129 } else {

130 assert(ST->is64Bit());

131 Last = UseInst;

132

133 Register LastOp1Reg = Last->getOperand(1).getReg();

134 if (!LastOp1Reg.isVirtual())

135 return false;

136 Hi12 = MRI->getVRegDef(LastOp1Reg);

137 const MachineOperand &Hi12Op2 = Hi12->getOperand(2);

138 if (Hi12Op2.getTargetFlags() != LoongArchII::MO_PCREL64_HI)

139 return false;

140 if (!isGlobalOrCPIOrBlockAddress(Hi12Op2) || Hi12Op2.getOffset() != 0)

141 return false;

142 if (!MRI->hasOneUse(Hi12->getOperand(0).getReg()))

143 return false;

144

145 Lo20 = MRI->getVRegDef(Hi12->getOperand(1).getReg());

146 const MachineOperand &Lo20Op2 = Lo20->getOperand(2);

147 if (Lo20Op2.getTargetFlags() != LoongArchII::MO_PCREL64_LO)

148 return false;

149 if (!isGlobalOrCPIOrBlockAddress(Lo20Op2) || Lo20Op2.getOffset() != 0)

150 return false;

151 if (!MRI->hasOneUse(Lo20->getOperand(0).getReg()))

152 return false;

153

154 Lo12 = MRI->getVRegDef(Lo20->getOperand(1).getReg());

155 if (!MRI->hasOneUse(Lo12->getOperand(0).getReg()))

156 return false;

157 }

158

160 assert(Hi20.getOpcode() == LoongArch::PCALAU12I);

162 !(isGlobalOrCPIOrBlockAddress(Lo12Op2) || Lo12Op2.isMCSymbol()) ||

163 Lo12Op2.getOffset() != 0)

164 return false;

165

166 if (Hi20Op1.isGlobal()) {

167 LLVM_DEBUG(dbgs() << " Found lowered global address: "

168 << *Hi20Op1.getGlobal() << "\n");

169 } else if (Hi20Op1.isBlockAddress()) {

170 LLVM_DEBUG(dbgs() << " Found lowered basic address: "

171 << *Hi20Op1.getBlockAddress() << "\n");

172 } else if (Hi20Op1.isCPI()) {

173 LLVM_DEBUG(dbgs() << " Found lowered constant pool: " << Hi20Op1.getIndex()

174 << "\n");

175 }

176

177 return true;

178}

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193

194bool LoongArchMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi20,

197 if (Hi20.getOpcode() != LoongArch::LU12I_W)

198 return false;

199

200 auto isGlobalOrCPI = [](const MachineOperand &Op) {

201 return Op.isGlobal() || Op.isCPI();

202 };

203

204 const MachineOperand &Hi20Op1 = Hi20.getOperand(1);

206 !isGlobalOrCPI(Hi20Op1) || Hi20Op1.getOffset() != 0)

207 return false;

208

210 if ( MRI ->hasOneUse(HiDestReg))

211 return false;

212

213 Add = &*MRI->use_instr_begin(HiDestReg);

214 if ((ST->is64Bit() && Add->getOpcode() != LoongArch::PseudoAddTPRel_D) ||

215 (!ST->is64Bit() && Add->getOpcode() != LoongArch::PseudoAddTPRel_W))

216 return false;

217

218 if (Add->getOperand(2).getReg() != LoongArch::R2)

219 return false;

220

221 const MachineOperand &AddOp3 = Add->getOperand(3);

223 !(isGlobalOrCPI(AddOp3) || AddOp3.isMCSymbol()) ||

225 return false;

226

227 Register AddDestReg = Add->getOperand(0).getReg();

228 if ( MRI ->hasOneUse(AddDestReg))

229 return false;

230

231 Lo12 = &*MRI->use_instr_begin(AddDestReg);

232 if ((ST->is64Bit() && Lo12->getOpcode() != LoongArch::ADDI_D) ||

234 return false;

235

236 const MachineOperand &Lo12Op2 = Lo12->getOperand(2);

238 !(isGlobalOrCPI(Lo12Op2) || Lo12Op2.isMCSymbol()) ||

240 return false;

241

243 LLVM_DEBUG(dbgs() << " Found lowered global address: "

244 << *Hi20Op1.getGlobal() << "\n");

245 } else if (Hi20Op1.isCPI()) {

247 << "\n");

248 }

249

250 return true;

251}

252

253

254

255

256void LoongArchMergeBaseOffsetOpt::foldOffset(

257 MachineInstr &Hi20, MachineInstr &Lo12, MachineInstr *&Lo20,

258 MachineInstr *&Hi12, MachineInstr *&Last, MachineInstr &Tail,

260

263 if (Lo20 && Hi12) {

266 }

267

268

269

271 if (Hi20.getOpcode() == LoongArch::LU12I_W)

272 Add->getOperand(3).setOffset(Offset);

273

274

276 MRI->constrainRegClass(Def->getOperand(0).getReg(),

277 MRI->getRegClass(Tail.getOperand(0).getReg()));

278 MRI->replaceRegWith(Tail.getOperand(0).getReg(), Def->getOperand(0).getReg());

279 Tail.eraseFromParent();

280

282 << " " << Hi20;);

283 if (Hi20.getOpcode() == LoongArch::LU12I_W) {

285 }

287 if (Lo20 && Hi12) {

289 }

290}

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332bool LoongArchMergeBaseOffsetOpt::foldLargeOffset(

333 MachineInstr &Hi20, MachineInstr &Lo12, MachineInstr *&Lo20,

334 MachineInstr *&Hi12, MachineInstr *&Last, MachineInstr &TailAdd,

337 TailAdd.getOpcode() == LoongArch::ADD_D) &&

338 "Expected ADD instruction!");

342 SmallVector<MachineInstr *, 4> Instrs;

344 int64_t Mask = -1;

345

346

347 for (int i = 0; i < 4; i++) {

348

349 if (Reg == LoongArch::R0)

350 break;

351

352

354 return false;

355

356 MachineInstr *Curr = MRI->getVRegDef(Reg);

357 if (!Curr)

358 break;

359

361 default:

362

363 return false;

364 case LoongArch::ORI: {

365 MachineOperand ImmOp = Curr->getOperand(2);

367 return false;

371 break;

372 }

373 case LoongArch::LU12I_W: {

374 MachineOperand ImmOp = Curr->getOperand(1);

376 return false;

378 Reg = LoongArch::R0;

380 break;

381 }

382 case LoongArch::LU32I_D: {

383 MachineOperand ImmOp = Curr->getOperand(2);

385 return false;

387 Mask ^= 0x000FFFFF00000000ULL;

390 break;

391 }

392 case LoongArch::LU52I_D: {

393 MachineOperand ImmOp = Curr->getOperand(2);

395 return false;

397 Mask ^= 0xFFF0000000000000ULL;

400 break;

401 }

402 }

403 }

404

405

407 return false;

408

409 foldOffset(Hi20, Lo12, Lo20, Hi12, Last, TailAdd, Offset);

411 for (auto I : Instrs) {

413 I->eraseFromParent();

414 }

415

416 return true;

417}

418

419bool LoongArchMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &Hi20,

420 MachineInstr &Lo12,

421 MachineInstr *&Lo20,

422 MachineInstr *&Hi12,

423 MachineInstr *&Last) {

426

427

428

429

430

431 if ( MRI ->hasOneUse(DestReg))

432 return false;

433

434

435 MachineInstr &Tail = *MRI->use_instr_begin(DestReg);

436 switch (Tail.getOpcode()) {

437 default:

438 LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:"

440 break;

441 case LoongArch::ADDI_W:

443 return false;

444 [[fallthrough]];

445 case LoongArch::ADDI_D:

446 case LoongArch::ADDU16I_D: {

447

448 int64_t Offset = Tail.getOperand(2).getImm();

449 if (Tail.getOpcode() == LoongArch::ADDU16I_D)

451

452

453 Register TailDestReg = Tail.getOperand(0).getReg();

454 if (MRI->hasOneUse(TailDestReg)) {

455 MachineInstr &TailTail = *MRI->use_instr_begin(TailDestReg);

456 if (ST->is64Bit() && TailTail.getOpcode() == LoongArch::ADDI_W)

457 return false;

458 if (TailTail.getOpcode() == LoongArch::ADDI_W ||

459 TailTail.getOpcode() == LoongArch::ADDI_D) {

462 foldOffset(Hi20, Lo12, Lo20, Hi12, Last, TailTail, Offset);

463 Tail.eraseFromParent();

464 return true;

465 }

466 }

467

469 foldOffset(Hi20, Lo12, Lo20, Hi12, Last, Tail, Offset);

470 return true;

471 }

472 case LoongArch::ADD_W:

474 return false;

475 [[fallthrough]];

476 case LoongArch::ADD_D:

477

478 return foldLargeOffset(Hi20, Lo12, Lo20, Hi12, Last, Tail, DestReg);

479 break;

480 }

481

482 return false;

483}

484

485

486static unsigned getNewOpc(unsigned Op, bool isLarge) {

487 switch (Op) {

488 case LoongArch::LD_B:

489 return isLarge ? LoongArch::LDX_B : LoongArch::LD_B;

490 case LoongArch::LD_H:

491 return isLarge ? LoongArch::LDX_H : LoongArch::LD_H;

492 case LoongArch::LD_W:

493 case LoongArch::LDPTR_W:

494 return isLarge ? LoongArch::LDX_W : LoongArch::LD_W;

495 case LoongArch::LD_D:

496 case LoongArch::LDPTR_D:

497 return isLarge ? LoongArch::LDX_D : LoongArch::LD_D;

498 case LoongArch::LD_BU:

499 return isLarge ? LoongArch::LDX_BU : LoongArch::LD_BU;

500 case LoongArch::LD_HU:

501 return isLarge ? LoongArch::LDX_HU : LoongArch::LD_HU;

502 case LoongArch::LD_WU:

503 return isLarge ? LoongArch::LDX_WU : LoongArch::LD_WU;

504 case LoongArch::FLD_S:

505 return isLarge ? LoongArch::FLDX_S : LoongArch::FLD_S;

506 case LoongArch::FLD_D:

507 return isLarge ? LoongArch::FLDX_D : LoongArch::FLD_D;

508 case LoongArch::VLD:

509 return isLarge ? LoongArch::VLDX : LoongArch::VLD;

510 case LoongArch::XVLD:

511 return isLarge ? LoongArch::XVLDX : LoongArch::XVLD;

512 case LoongArch::VLDREPL_B:

513 return LoongArch::VLDREPL_B;

514 case LoongArch::XVLDREPL_B:

515 return LoongArch::XVLDREPL_B;

516 case LoongArch::ST_B:

517 return isLarge ? LoongArch::STX_B : LoongArch::ST_B;

518 case LoongArch::ST_H:

519 return isLarge ? LoongArch::STX_H : LoongArch::ST_H;

520 case LoongArch::ST_W:

521 case LoongArch::STPTR_W:

522 return isLarge ? LoongArch::STX_W : LoongArch::ST_W;

523 case LoongArch::ST_D:

524 case LoongArch::STPTR_D:

525 return isLarge ? LoongArch::STX_D : LoongArch::ST_D;

526 case LoongArch::FST_S:

527 return isLarge ? LoongArch::FSTX_S : LoongArch::FST_S;

528 case LoongArch::FST_D:

529 return isLarge ? LoongArch::FSTX_D : LoongArch::FST_D;

530 case LoongArch::VST:

531 return isLarge ? LoongArch::VSTX : LoongArch::VST;

532 case LoongArch::XVST:

533 return isLarge ? LoongArch::XVSTX : LoongArch::XVST;

534 default:

536 }

537}

538

539bool LoongArchMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi20,

540 MachineInstr &Lo12,

541 MachineInstr *&Lo20,

542 MachineInstr *&Hi12,

543 MachineInstr *&Last) {

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588 std::optional<int64_t> CommonOffset;

589 DenseMap<const MachineInstr *, SmallVector>

590 InlineAsmMemoryOpIndexesMap;

591 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) {

592 switch (UseMI.getOpcode()) {

593 default:

595 return false;

596 case LoongArch::VLDREPL_B:

597 case LoongArch::XVLDREPL_B:

598

600 return false;

601 [[fallthrough]];

602 case LoongArch::LD_B:

603 case LoongArch::LD_H:

604 case LoongArch::LD_W:

605 case LoongArch::LD_D:

606 case LoongArch::LD_BU:

607 case LoongArch::LD_HU:

608 case LoongArch::LD_WU:

609 case LoongArch::LDPTR_W:

610 case LoongArch::LDPTR_D:

611 case LoongArch::FLD_S:

612 case LoongArch::FLD_D:

613 case LoongArch::VLD:

614 case LoongArch::XVLD:

615 case LoongArch::ST_B:

616 case LoongArch::ST_H:

617 case LoongArch::ST_W:

618 case LoongArch::ST_D:

619 case LoongArch::STPTR_W:

620 case LoongArch::STPTR_D:

621 case LoongArch::FST_S:

622 case LoongArch::FST_D:

623 case LoongArch::VST:

624 case LoongArch::XVST: {

625 if (UseMI.getOperand(1).isFI())

626 return false;

627

628 if (DestReg == UseMI.getOperand(0).getReg())

629 return false;

631 "Expected base address use");

632

633 int64_t Offset = UseMI.getOperand(2).getImm();

634 if (CommonOffset && Offset != CommonOffset)

635 return false;

636 CommonOffset = Offset;

637 break;

638 }

639 case LoongArch::INLINEASM:

640 case LoongArch::INLINEASM_BR: {

641

643 return false;

644 SmallVector InlineAsmMemoryOpIndexes;

648 const MachineOperand &FlagsMO = UseMI.getOperand(I);

649

650 if (!FlagsMO.isImm())

651 continue;

652

653 const InlineAsm::Flag Flags(FlagsMO.getImm());

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659

660 for (unsigned J = 0; J < NumOps; ++J) {

661 const MachineOperand &MO = UseMI.getOperand(I + 1 + J);

662 if (MO.isReg() && MO.getReg() == DestReg)

663 return false;

664 }

665 continue;

666 }

667

668

669 if (Flags.getMemoryConstraintID() != InlineAsm::ConstraintCode::m)

670 return false;

671

672 const MachineOperand &AddrMO = UseMI.getOperand(I + 1);

673 if (!AddrMO.isReg() || AddrMO.getReg() != DestReg)

674 continue;

675

676 const MachineOperand &OffsetMO = UseMI.getOperand(I + 2);

677 if (!OffsetMO.isImm())

678 continue;

679

680

682 if (CommonOffset && Offset != CommonOffset)

683 return false;

684 CommonOffset = Offset;

685 InlineAsmMemoryOpIndexes.push_back(I + 1);

686 }

687 InlineAsmMemoryOpIndexesMap.insert(

688 std::make_pair(&UseMI, InlineAsmMemoryOpIndexes));

689 break;

690 }

691 }

692 }

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704 return false;

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724 MachineOperand &ImmOp = Lo12.getOperand(2);

726 if (Lo20 && Hi12) {

729 }

730 if (Hi20.getOpcode() == LoongArch::PCALAU12I) {

734 } else if (Hi20.getOpcode() == LoongArch::LU12I_W) {

736 Add->getOperand(3).setOffset(NewOffset);

737 }

738

739

741 for (MachineInstr &UseMI :

743 if (UseMI.getOpcode() == LoongArch::INLINEASM ||

744 UseMI.getOpcode() == LoongArch::INLINEASM_BR) {

745 auto &InlineAsmMemoryOpIndexes = InlineAsmMemoryOpIndexesMap[&UseMI];

746 for (unsigned I : InlineAsmMemoryOpIndexes) {

747 MachineOperand &MO = UseMI.getOperand(I + 1);

748 switch (ImmOp.getType()) {

752 break;

757 break;

761 break;

765 break;

766 default:

768 break;

769 }

770 }

771 } else {

774 UseMI.removeOperand(2);

775 UseMI.removeOperand(1);

776 UseMI.addOperand(Last->getOperand(1));

777 UseMI.addOperand(Last->getOperand(2));

778 UseMI.getOperand(1).setIsKill(false);

779 UseMI.getOperand(2).setIsKill(false);

780 } else {

781 UseMI.removeOperand(2);

782 UseMI.addOperand(ImmOp);

783 }

784 }

785 }

786

788 Last->eraseFromParent();

789 return true;

790 }

791

792 if (Hi20.getOpcode() == LoongArch::PCALAU12I) {

795 } else if (Hi20.getOpcode() == LoongArch::LU12I_W) {

798 Add->getOperand(0).getReg());

799 }

801 return true;

802}

803

804bool LoongArchMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {

806 return false;

807

809

810 bool MadeChange = false;

812 for (MachineBasicBlock &MBB : Fn) {

814 for (MachineInstr &Hi20 : MBB) {

815 MachineInstr *Lo12 = nullptr;

816 MachineInstr *Lo20 = nullptr;

817 MachineInstr *Hi12 = nullptr;

818 MachineInstr *Last = nullptr;

819 if (Hi20.getOpcode() == LoongArch::PCALAU12I) {

820

821 if (!detectFoldable(Hi20, Lo12, Lo20, Hi12, Last))

822 continue;

823 } else if (Hi20.getOpcode() == LoongArch::LU12I_W) {

824 MachineInstr *Add = nullptr;

825

826 if (!detectFoldable(Hi20, Add, Lo12))

827 continue;

828 } else {

829 continue;

830 }

831

832

833

834 MadeChange |= detectAndFoldOffset(Hi20, *Lo12, Lo20, Hi12, Last);

835 MadeChange |= foldIntoMemoryOps(Hi20, *Lo12, Lo20, Hi12, Last);

836 }

837 }

838

839 return MadeChange;

840}

841

842

844 return new LoongArchMergeBaseOffsetOpt();

845}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

static unsigned getNewOpc(unsigned Op, bool isLarge)

Definition LoongArchMergeBaseOffset.cpp:486

#define LoongArch_MERGE_BASE_OFFSET_NAME

Definition LoongArchMergeBaseOffset.cpp:26

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

Represent the analysis usage information of a pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)

FunctionPass class - This class is used to implement most global optimizations.

const LoongArchInstrInfo * getInstrInfo() const override

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

LLVM_ABI StringRef getName() const

Return the name of the corresponding LLVM basic block, or an empty string.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Properties which a MachineFunction may have at a given point in time.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Get the register for the operand index.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

const GlobalValue * getGlobal() const

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isCPI() const

isCPI - Tests if this is a MO_ConstantPoolIndex operand.

LLVM_ABI void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)

ChangeToMCSymbol - Replace this operand with a new MC symbol operand.

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

LLVM_ABI void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)

ChangeToGA - Replace this operand with a new global address operand.

LLVM_ABI void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)

ChangeToBA - Replace this operand with a new block address operand.

const BlockAddress * getBlockAddress() const

void setOffset(int64_t Offset)

unsigned getTargetFlags() const

bool isGlobal() const

isGlobal - Tests if this is a MO_GlobalAddress operand.

MachineOperandType getType() const

getType - Returns the MachineOperandType for this operand.

getReg - Returns the register number.

void setTargetFlags(unsigned F)

LLVM_ABI void ChangeToCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)

ChangeToCPI - Replace this operand with a new constant pool index operand.

MCSymbol * getMCSymbol() const

@ MO_ConstantPoolIndex

Address of indexed Constant in Constant Pool.

@ MO_MCSymbol

MCSymbol reference (for debug/eh info)

@ MO_GlobalAddress

Address of a global value.

@ MO_BlockAddress

Address of a basic block.

int64_t getOffset() const

Return the offset from the symbol in this operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

void push_back(const T &Elt)

StringRef - Represent a constant reference to a string, i.e.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Tail

Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...

static unsigned getDirectFlags(const MachineOperand &MO)

NodeAddr< DefNode * > Def

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

DWARFExpression::Operation Op

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

FunctionPass * createLoongArchMergeBaseOffsetOptPass()

Returns an instance of the Merge Base Offset Optimization pass.

Definition LoongArchMergeBaseOffset.cpp:843