LoongArchOptWInstrs.cpp Source File (original) (raw)

40using namespace llvm;

42#define DEBUG_TYPE "loongarch-opt-w-instrs"

43#define LOONGARCH_OPT_W_INSTRS_NAME "LoongArch Optimize W Instructions"

45 STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");

47 "Number of instructions transformed to W-ops");

51 cl::desc("Disable removal of sign-extend insn"),

55 cl::desc("Disable convert to D suffix"),

58namespace {

61public:

62 static char ID;

66 bool runOnMachineFunction(MachineFunction &MF) override;

67 bool removeSExtWInstrs(MachineFunction &MF, const LoongArchInstrInfo &TII,

68 const LoongArchSubtarget &ST,

69 MachineRegisterInfo &MRI);

70 bool convertToDSuffixes(MachineFunction &MF, const LoongArchInstrInfo &TII,

71 const LoongArchSubtarget &ST,

72 MachineRegisterInfo &MRI);

73 bool convertToWSuffixes(MachineFunction &MF, const LoongArchInstrInfo &TII,

74 const LoongArchSubtarget &ST,

75 MachineRegisterInfo &MRI);

77 void getAnalysisUsage(AnalysisUsage &AU) const override {

80 }

83};

85}

87char LoongArchOptWInstrs::ID = 0;

89 false, false)

92 return new LoongArchOptWInstrs();

93}

101

104

105 Worklist.push_back(std::make_pair(&OrigMI, OrigBits));

106

107 while (!Worklist.empty()) {

110 unsigned Bits = P.second;

111

112 if (!Visited.insert(P).second)

113 continue;

114

115

116 if (MI->getNumExplicitDefs() != 1)

117 return false;

118

119 Register DestReg = MI->getOperand(0).getReg();

121 return false;

122

123 for (auto &UserOp : MRI.use_nodbg_operands(DestReg)) {

125 unsigned OpIdx = UserOp.getOperandNo();

126

128 default:

129 return false;

130

131 case LoongArch::ADD_W:

132 case LoongArch::ADDI_W:

133 case LoongArch::SUB_W:

134 case LoongArch::ALSL_W:

135 case LoongArch::ALSL_WU:

136 case LoongArch::MUL_W:

137 case LoongArch::MULH_W:

138 case LoongArch::MULH_WU:

139 case LoongArch::MULW_D_W:

140 case LoongArch::MULW_D_WU:

141 case LoongArch::SLL_W:

142 case LoongArch::SLLI_W:

143 case LoongArch::SRL_W:

144 case LoongArch::SRLI_W:

145 case LoongArch::SRA_W:

146 case LoongArch::SRAI_W:

147 case LoongArch::ROTR_W:

148 case LoongArch::ROTRI_W:

149 case LoongArch::CLO_W:

150 case LoongArch::CLZ_W:

151 case LoongArch::CTO_W:

152 case LoongArch::CTZ_W:

153 case LoongArch::BYTEPICK_W:

154 case LoongArch::REVB_2H:

155 case LoongArch::BITREV_4B:

156 case LoongArch::BITREV_W:

157 case LoongArch::BSTRINS_W:

158 case LoongArch::BSTRPICK_W:

159 case LoongArch::CRC_W_W_W:

160 case LoongArch::CRCC_W_W_W:

161 case LoongArch::MOVGR2FCSR:

162 case LoongArch::MOVGR2FRH_W:

163 case LoongArch::MOVGR2FR_W_64:

164 case LoongArch::VINSGR2VR_W:

165 case LoongArch::XVINSGR2VR_W:

166 case LoongArch::VREPLGR2VR_W:

167 case LoongArch::XVREPLGR2VR_W:

168 if (Bits >= 32)

169 break;

170 return false;

171

172

173 case LoongArch::DIV_W:

174 case LoongArch::DIV_WU:

175 case LoongArch::MOD_W:

176 case LoongArch::MOD_WU:

177 if (Bits >= 32 && ST.hasDiv32())

178 break;

179 return false;

180 case LoongArch::MOVGR2CF:

181 case LoongArch::VREPLVE_D:

182 case LoongArch::XVREPLVE_D:

183 if (Bits >= 1)

184 break;

185 return false;

186 case LoongArch::VREPLVE_W:

187 case LoongArch::XVREPLVE_W:

188 if (Bits >= 2)

189 break;

190 return false;

191 case LoongArch::VREPLVE_H:

192 case LoongArch::XVREPLVE_H:

193 if (Bits >= 3)

194 break;

195 return false;

196 case LoongArch::VREPLVE_B:

197 case LoongArch::XVREPLVE_B:

198 if (Bits >= 4)

199 break;

200 return false;

201 case LoongArch::EXT_W_B:

202 case LoongArch::VINSGR2VR_B:

203 case LoongArch::VREPLGR2VR_B:

204 case LoongArch::XVREPLGR2VR_B:

205 if (Bits >= 8)

206 break;

207 return false;

208 case LoongArch::EXT_W_H:

209 case LoongArch::VINSGR2VR_H:

210 case LoongArch::VREPLGR2VR_H:

211 case LoongArch::XVREPLGR2VR_H:

212 if (Bits >= 16)

213 break;

214 return false;

215

216 case LoongArch::SRLI_D: {

217

218

219

221 if (Bits > ShAmt) {

222 Worklist.push_back(std::make_pair(UserMI, Bits - ShAmt));

223 break;

224 }

225 return false;

226 }

227

228

229

230 case LoongArch::SLLI_D:

231 if (Bits >= (ST.getGRLen() - UserMI->getOperand(2).getImm()))

232 break;

233 Worklist.push_back(std::make_pair(UserMI, Bits));

234 break;

235 case LoongArch::ANDI: {

238 break;

239 Worklist.push_back(std::make_pair(UserMI, Bits));

240 break;

241 }

242 case LoongArch::ORI: {

245 break;

246 Worklist.push_back(std::make_pair(UserMI, Bits));

247 break;

248 }

249

250 case LoongArch::SLL_D:

251

252 if (OpIdx == 2) {

253 if (Bits >= Log2_32(ST.getGRLen()))

254 break;

255 return false;

256 }

257 Worklist.push_back(std::make_pair(UserMI, Bits));

258 break;

259

260 case LoongArch::SRA_D:

261 case LoongArch::SRL_D:

262 case LoongArch::ROTR_D:

263

264 if (OpIdx == 2 && Bits >= Log2_32(ST.getGRLen()))

265 break;

266 return false;

267

268 case LoongArch::ST_B:

269 case LoongArch::STX_B:

270 case LoongArch::STGT_B:

271 case LoongArch::STLE_B:

272 case LoongArch::IOCSRWR_B:

273

274 if (OpIdx == 0 && Bits >= 8)

275 break;

276 return false;

277 case LoongArch::ST_H:

278 case LoongArch::STX_H:

279 case LoongArch::STGT_H:

280 case LoongArch::STLE_H:

281 case LoongArch::IOCSRWR_H:

282

283 if (OpIdx == 0 && Bits >= 16)

284 break;

285 return false;

286 case LoongArch::ST_W:

287 case LoongArch::STX_W:

288 case LoongArch::SCREL_W:

289 case LoongArch::STPTR_W:

290 case LoongArch::STGT_W:

291 case LoongArch::STLE_W:

292 case LoongArch::IOCSRWR_W:

293

294 if (OpIdx == 0 && Bits >= 32)

295 break;

296 return false;

297

298 case LoongArch::CRC_W_B_W:

299 case LoongArch::CRCC_W_B_W:

300 if ((OpIdx == 1 && Bits >= 8) || (OpIdx == 2 && Bits >= 32))

301 break;

302 return false;

303 case LoongArch::CRC_W_H_W:

304 case LoongArch::CRCC_W_H_W:

305 if ((OpIdx == 1 && Bits >= 16) || (OpIdx == 2 && Bits >= 32))

306 break;

307 return false;

308 case LoongArch::CRC_W_D_W:

309 case LoongArch::CRCC_W_D_W:

310 if (OpIdx == 2 && Bits >= 32)

311 break;

312 return false;

313

314

315

316 case LoongArch::COPY:

317 case LoongArch::PHI:

318 case LoongArch::ADD_D:

319 case LoongArch::ADDI_D:

320 case LoongArch::SUB_D:

321 case LoongArch::MUL_D:

322 case LoongArch::AND:

323 case LoongArch::OR:

324 case LoongArch::NOR:

325 case LoongArch::XOR:

326 case LoongArch::XORI:

327 case LoongArch::ANDN:

328 case LoongArch::ORN:

329 Worklist.push_back(std::make_pair(UserMI, Bits));

330 break;

331

332 case LoongArch::MASKNEZ:

333 case LoongArch::MASKEQZ:

335 return false;

336 Worklist.push_back(std::make_pair(UserMI, Bits));

337 break;

338 }

339 }

340 }

341

342 return true;

343}

344

350

351

352

355 switch (MI.getOpcode()) {

356

357 case LoongArch::ADD_W:

358 case LoongArch::SUB_W:

359 case LoongArch::ADDI_W:

360 case LoongArch::ALSL_W:

361 case LoongArch::LU12I_W:

362 case LoongArch::SLT:

363 case LoongArch::SLTU:

364 case LoongArch::SLTI:

365 case LoongArch::SLTUI:

366 case LoongArch::ANDI:

367 case LoongArch::MUL_W:

368 case LoongArch::MULH_W:

369 case LoongArch::MULH_WU:

370 case LoongArch::DIV_W:

371 case LoongArch::MOD_W:

372 case LoongArch::DIV_WU:

373 case LoongArch::MOD_WU:

374 case LoongArch::SLL_W:

375 case LoongArch::SRL_W:

376 case LoongArch::SRA_W:

377 case LoongArch::ROTR_W:

378 case LoongArch::SLLI_W:

379 case LoongArch::SRLI_W:

380 case LoongArch::SRAI_W:

381 case LoongArch::ROTRI_W:

382 case LoongArch::EXT_W_B:

383 case LoongArch::EXT_W_H:

384 case LoongArch::CLO_W:

385 case LoongArch::CLZ_W:

386 case LoongArch::CTO_W:

387 case LoongArch::CTZ_W:

388 case LoongArch::BYTEPICK_W:

389 case LoongArch::REVB_2H:

390 case LoongArch::BITREV_4B:

391 case LoongArch::BITREV_W:

392 case LoongArch::BSTRINS_W:

393 case LoongArch::BSTRPICK_W:

394 case LoongArch::LD_B:

395 case LoongArch::LD_H:

396 case LoongArch::LD_W:

397 case LoongArch::LD_BU:

398 case LoongArch::LD_HU:

399 case LoongArch::LL_W:

400 case LoongArch::LLACQ_W:

401 case LoongArch::RDTIMEL_W:

402 case LoongArch::RDTIMEH_W:

403 case LoongArch::CPUCFG:

404 case LoongArch::LDX_B:

405 case LoongArch::LDX_H:

406 case LoongArch::LDX_W:

407 case LoongArch::LDX_BU:

408 case LoongArch::LDX_HU:

409 case LoongArch::LDPTR_W:

410 case LoongArch::LDGT_B:

411 case LoongArch::LDGT_H:

412 case LoongArch::LDGT_W:

413 case LoongArch::LDLE_B:

414 case LoongArch::LDLE_H:

415 case LoongArch::LDLE_W:

416 case LoongArch::AMSWAP_B:

417 case LoongArch::AMSWAP_H:

418 case LoongArch::AMSWAP_W:

419 case LoongArch::AMADD_B:

420 case LoongArch::AMADD_H:

421 case LoongArch::AMADD_W:

422 case LoongArch::AMAND_W:

423 case LoongArch::AMOR_W:

424 case LoongArch::AMXOR_W:

425 case LoongArch::AMMAX_W:

426 case LoongArch::AMMIN_W:

427 case LoongArch::AMMAX_WU:

428 case LoongArch::AMMIN_WU:

429 case LoongArch::AMSWAP__DB_B:

430 case LoongArch::AMSWAP__DB_H:

431 case LoongArch::AMSWAP__DB_W:

432 case LoongArch::AMADD__DB_B:

433 case LoongArch::AMADD__DB_H:

434 case LoongArch::AMADD__DB_W:

435 case LoongArch::AMAND__DB_W:

436 case LoongArch::AMOR__DB_W:

437 case LoongArch::AMXOR__DB_W:

438 case LoongArch::AMMAX__DB_W:

439 case LoongArch::AMMIN__DB_W:

440 case LoongArch::AMMAX__DB_WU:

441 case LoongArch::AMMIN__DB_WU:

442 case LoongArch::AMCAS_B:

443 case LoongArch::AMCAS_H:

444 case LoongArch::AMCAS_W:

445 case LoongArch::AMCAS__DB_B:

446 case LoongArch::AMCAS__DB_H:

447 case LoongArch::AMCAS__DB_W:

448 case LoongArch::CRC_W_B_W:

449 case LoongArch::CRC_W_H_W:

450 case LoongArch::CRC_W_W_W:

451 case LoongArch::CRC_W_D_W:

452 case LoongArch::CRCC_W_B_W:

453 case LoongArch::CRCC_W_H_W:

454 case LoongArch::CRCC_W_W_W:

455 case LoongArch::CRCC_W_D_W:

456 case LoongArch::IOCSRRD_B:

457 case LoongArch::IOCSRRD_H:

458 case LoongArch::IOCSRRD_W:

459 case LoongArch::MOVFR2GR_S:

460 case LoongArch::MOVFCSR2GR:

461 case LoongArch::MOVCF2GR:

462 case LoongArch::MOVFRH2GR_S:

463 case LoongArch::MOVFR2GR_S_64:

464 case LoongArch::VPICKVE2GR_W:

465 case LoongArch::XVPICKVE2GR_W:

466 return true;

467

468

469 case LoongArch::SRAI_D:

470 return MI.getOperand(2).getImm() >= 32;

471 case LoongArch::SRLI_D:

472 return MI.getOperand(2).getImm() > 32;

473

474 case LoongArch::ADDI_D:

475 case LoongArch::ORI:

476 return MI.getOperand(1).isReg() &&

477 MI.getOperand(1).getReg() == LoongArch::R0;

478

479 case LoongArch::BSTRPICK_D:

480 return MI.getOperand(2).getImm() < 31;

481

482 case LoongArch::COPY:

483 return MI.getOperand(1).getReg() == LoongArch::R0;

484

485 case LoongArch::PseudoMaskedAtomicSwap32:

486 case LoongArch::PseudoAtomicSwap32:

487 case LoongArch::PseudoMaskedAtomicLoadAdd32:

488 case LoongArch::PseudoMaskedAtomicLoadSub32:

489 case LoongArch::PseudoAtomicLoadNand32:

490 case LoongArch::PseudoMaskedAtomicLoadNand32:

491 case LoongArch::PseudoAtomicLoadAdd32:

492 case LoongArch::PseudoAtomicLoadSub32:

493 case LoongArch::PseudoAtomicLoadAnd32:

494 case LoongArch::PseudoAtomicLoadOr32:

495 case LoongArch::PseudoAtomicLoadXor32:

496 case LoongArch::PseudoMaskedAtomicLoadUMax32:

497 case LoongArch::PseudoMaskedAtomicLoadUMin32:

498 case LoongArch::PseudoCmpXchg32:

499 case LoongArch::PseudoMaskedCmpXchg32:

500 case LoongArch::PseudoMaskedAtomicLoadMax32:

501 case LoongArch::PseudoMaskedAtomicLoadMin32:

502 return OpNo == 0;

503 }

504

505 return false;

506}

507

513

514 auto AddRegToWorkList = [&](Register SrcReg) {

516 return false;

518 return true;

519 };

520

521 if (!AddRegToWorkList(SrcReg))

522 return false;

523

524 while (!Worklist.empty()) {

526

527

529 continue;

530

532 if ()

533 continue;

534

535 int OpNo = MI->findRegisterDefOperandIdx(Reg, nullptr);

536 assert(OpNo != -1 && "Couldn't find register");

537

538

540 continue;

541

542

543 switch (MI->getOpcode()) {

544 default:

545

546 return false;

547 case LoongArch::COPY: {

551

552

553

554 if (MI->getParent() == &MF->front()) {

555 Register VReg = MI->getOperand(0).getReg();

557 continue;

558 }

559

560 Register CopySrcReg = MI->getOperand(1).getReg();

561 if (CopySrcReg == LoongArch::R4) {

562

563

564

565

566

567

568

569

571 auto II = MI->getIterator();

572 if (II == MBB->instr_begin() ||

573 (--II)->getOpcode() != LoongArch::ADJCALLSTACKUP)

574 return false;

575

578 return false;

579

580 auto *CalleeFn =

582 if (!CalleeFn)

583 return false;

584

586 if (!IntTy)

587 return false;

588

589 const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();

590 unsigned BitWidth = IntTy->getBitWidth();

591 if ((BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||

592 (BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt)))

593 continue;

594 }

595

596 if (!AddRegToWorkList(CopySrcReg))

597 return false;

598

599 break;

600 }

601

602

603 case LoongArch::MOD_D:

604 case LoongArch::ANDI:

605 case LoongArch::ORI:

606 case LoongArch::XORI:

607

608

609

610 if (!AddRegToWorkList(MI->getOperand(1).getReg()))

611 return false;

612

613 break;

614 case LoongArch::MOD_DU:

615 case LoongArch::AND:

616 case LoongArch::OR:

617 case LoongArch::XOR:

618 case LoongArch::ANDN:

619 case LoongArch::ORN:

620 case LoongArch::PHI: {

621

622

623

624

625

626 unsigned B = 1, E = 3, D = 1;

627 switch (MI->getOpcode()) {

628 case LoongArch::PHI:

629 E = MI->getNumOperands();

630 D = 2;

631 break;

632 }

633

634 for (unsigned I = B; I != E; I += D) {

635 if (->getOperand(I).isReg())

636 return false;

637

638 if (!AddRegToWorkList(MI->getOperand(I).getReg()))

639 return false;

640 }

641

642 break;

643 }

644

645 case LoongArch::MASKEQZ:

646 case LoongArch::MASKNEZ:

647

648

649 if (!AddRegToWorkList(MI->getOperand(1).getReg()))

650 return false;

651 break;

652

653

654

655 case LoongArch::SLLI_D:

656

657 if (MI->getOperand(2).getImm() >= 32)

658 return false;

659 [[fallthrough]];

660 case LoongArch::ADDI_D:

661 case LoongArch::ADD_D:

662 case LoongArch::LD_D:

663 case LoongArch::LD_WU:

664 case LoongArch::MUL_D:

665 case LoongArch::SUB_D:

668 break;

669 }

670 return false;

671

672

673 case LoongArch::DIV_D: {

674 if (!AddRegToWorkList(MI->getOperand(1).getReg()))

675 return false;

676 if (!AddRegToWorkList(MI->getOperand(2).getReg()))

677 return false;

680 break;

681 }

682 return false;

683 }

684 }

685 }

686

687

688

689 return true;

690}

691

692static unsigned getWOp(unsigned Opcode) {

693 switch (Opcode) {

694 case LoongArch::ADDI_D:

695 return LoongArch::ADDI_W;

696 case LoongArch::ADD_D:

697 return LoongArch::ADD_W;

698 case LoongArch::DIV_D:

699 return LoongArch::DIV_W;

700 case LoongArch::LD_D:

701 case LoongArch::LD_WU:

702 return LoongArch::LD_W;

703 case LoongArch::MUL_D:

704 return LoongArch::MUL_W;

705 case LoongArch::SLLI_D:

706 return LoongArch::SLLI_W;

707 case LoongArch::SUB_D:

708 return LoongArch::SUB_W;

709 default:

710 llvm_unreachable("Unexpected opcode for replacement with W variant");

711 }

712}

713

714bool LoongArchOptWInstrs::removeSExtWInstrs(MachineFunction &MF,

719 return false;

720

721 bool MadeChange = false;

722 for (MachineBasicBlock &MBB : MF) {

724

726 continue;

727

728 Register SrcReg = MI.getOperand(1).getReg();

729

730 SmallPtrSet<MachineInstr *, 4> FixableDefs;

731

732

733

734

737 continue;

738

739 Register DstReg = MI.getOperand(0).getReg();

740 if ( MRI .constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))

741 continue;

742

743

744 for (MachineInstr *Fixable : FixableDefs) {

746 Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));

747 Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);

748 Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);

749 Fixable->clearFlag(MachineInstr::MIFlag::IsExact);

751 ++NumTransformedToWInstrs;

752 }

753

754 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");

755 MRI.replaceRegWith(DstReg, SrcReg);

756 MRI.clearKillFlags(SrcReg);

757 MI.eraseFromParent();

758 ++NumRemovedSExtW;

759 MadeChange = true;

760 }

761 }

762

763 return MadeChange;

764}

765

766bool LoongArchOptWInstrs::convertToDSuffixes(MachineFunction &MF,

767 const LoongArchInstrInfo &TII,

768 const LoongArchSubtarget &ST,

769 MachineRegisterInfo &MRI) {

770 bool MadeChange = false;

771 for (MachineBasicBlock &MBB : MF) {

772 for (MachineInstr &MI : MBB) {

773 unsigned Opc;

774 switch (MI.getOpcode()) {

775 default:

776 continue;

777 case LoongArch::ADDI_W:

778 Opc = LoongArch::ADDI_D;

779 break;

780 }

781

784 MadeChange = true;

785 }

786 }

787 }

788

789 return MadeChange;

790}

791

792bool LoongArchOptWInstrs::convertToWSuffixes(MachineFunction &MF,

793 const LoongArchInstrInfo &TII,

794 const LoongArchSubtarget &ST,

795 MachineRegisterInfo &MRI) {

796 bool MadeChange = false;

797 for (MachineBasicBlock &MBB : MF) {

798 for (MachineInstr &MI : MBB) {

799 unsigned WOpc;

800

801 switch (MI.getOpcode()) {

802 default:

803 continue;

804 case LoongArch::ADD_D:

805 WOpc = LoongArch::ADD_W;

806 break;

807 case LoongArch::ADDI_D:

808 WOpc = LoongArch::ADDI_W;

809 break;

810 case LoongArch::SUB_D:

811 WOpc = LoongArch::SUB_W;

812 break;

813 case LoongArch::MUL_D:

814 WOpc = LoongArch::MUL_W;

815 break;

816 case LoongArch::SLLI_D:

817

818 if (MI.getOperand(2).getImm() >= 32)

819 continue;

820 WOpc = LoongArch::SLLI_W;

821 break;

822 case LoongArch::LD_D:

823 case LoongArch::LD_WU:

824 WOpc = LoongArch::LD_W;

825 break;

826 }

827

831 MI.clearFlag(MachineInstr::MIFlag::NoSWrap);

832 MI.clearFlag(MachineInstr::MIFlag::NoUWrap);

833 MI.clearFlag(MachineInstr::MIFlag::IsExact);

835 ++NumTransformedToWInstrs;

836 MadeChange = true;

837 }

838 }

839 }

840

841 return MadeChange;

842}

843

844bool LoongArchOptWInstrs::runOnMachineFunction(MachineFunction &MF) {

846 return false;

847

849 const LoongArchSubtarget &ST = MF.getSubtarget();

850 const LoongArchInstrInfo &TII = *ST.getInstrInfo();

851

852 if (.is64Bit())

853 return false;

854

855 bool MadeChange = false;

856 MadeChange |= removeSExtWInstrs(MF, TII, ST, MRI);

857

859 MadeChange |= convertToDSuffixes(MF, TII, ST, MRI);

860

861 if (ST.preferWInst())

862 MadeChange |= convertToWSuffixes(MF, TII, ST, MRI);

863

864 return MadeChange;

865}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

static bool isSignExtendingOpW(const MachineInstr &MI, const MachineRegisterInfo &MRI, unsigned OpNo)

Definition LoongArchOptWInstrs.cpp:353

static cl::opt< bool > DisableSExtWRemoval("loongarch-disable-sextw-removal", cl::desc("Disable removal of sign-extend insn"), cl::init(false), cl::Hidden)

static bool hasAllWUsers(const MachineInstr &OrigMI, const LoongArchSubtarget &ST, const MachineRegisterInfo &MRI)

Definition LoongArchOptWInstrs.cpp:345

static bool isSignExtendedW(Register SrcReg, const LoongArchSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)

Definition LoongArchOptWInstrs.cpp:508

#define LOONGARCH_OPT_W_INSTRS_NAME

Definition LoongArchOptWInstrs.cpp:43

static bool hasAllNBitUsers(const MachineInstr &OrigMI, const LoongArchSubtarget &ST, const MachineRegisterInfo &MRI, unsigned OrigBits)

Definition LoongArchOptWInstrs.cpp:98

static unsigned getWOp(unsigned Opcode)

Definition LoongArchOptWInstrs.cpp:692

static cl::opt< bool > DisableCvtToDSuffix("loongarch-disable-cvt-to-d-suffix", cl::desc("Disable convert to D suffix"), cl::init(false), cl::Hidden)

Promote Memory to Register

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

This file defines the SmallSet class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

This class holds the attributes for a particular argument, parameter, function, or return value.

FunctionPass class - This class is used to implement most global optimizations.

LoongArchMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private Lo...

bool isSExt32Register(Register Reg) const

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineBasicBlock & front() const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

bool isCall(QueryType Type=AnyInBundle) const

const MachineOperand & getOperand(unsigned i) const

const GlobalValue * getGlobal() const

bool isGlobal() const

isGlobal - Tests if this is a MO_GlobalAddress operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

LLVM_ABI bool isLiveIn(Register Reg) const

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

bool isSEXT_W(const MachineInstr &MI)

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

auto dyn_cast_if_present(const Y &Val)

dyn_cast_if_present - Functionally identical to dyn_cast, except that a null (or none in the case ...

int bit_width(T Value)

Returns the number of bits needed to represent Value if Value is nonzero.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

unsigned Log2_32(uint32_t Value)

Return the floor log base 2 of the specified value, -1 if the value is zero.

FunctionPass * createLoongArchOptWInstrsPass()

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr unsigned BitWidth