LLVM: lib/Target/M68k/M68kInstrInfo.h Source File (original) (raw)
1
2
3
4
5
6
7
8
9
10
11
12
13
14#ifndef LLVM_LIB_TARGET_M68K_M68KINSTRINFO_H
15#define LLVM_LIB_TARGET_M68K_M68KINSTRINFO_H
16
19
21
24
25#define GET_INSTRINFO_HEADER
26#include "M68kGenInstrInfo.inc"
27
28namespace llvm {
29
30class M68kSubtarget;
31
32namespace M68k {
33
54
55
56
57
59 switch (CC) {
60 default:
94 }
95}
96
98 switch (CC) {
99 default:
102 return M68k::Beq8;
104 return M68k::Bne8;
106 return M68k::Blt8;
108 return M68k::Ble8;
110 return M68k::Bgt8;
112 return M68k::Bge8;
114 return M68k::Bcs8;
116 return M68k::Bls8;
118 return M68k::Bhi8;
120 return M68k::Bcc8;
122 return M68k::Bmi8;
124 return M68k::Bpl8;
126 return M68k::Bvs8;
128 return M68k::Bvc8;
129 }
130}
131
133 switch (Opcode) {
134 default:
136 case M68k::Beq8:
138 case M68k::Bne8:
140 case M68k::Blt8:
142 case M68k::Ble8:
144 case M68k::Bgt8:
146 case M68k::Bge8:
148 case M68k::Bcs8:
150 case M68k::Bls8:
152 case M68k::Bhi8:
154 case M68k::Bcc8:
156 case M68k::Bmi8:
158 case M68k::Bpl8:
160 case M68k::Bvs8:
162 case M68k::Bvc8:
164 }
165}
166
167static inline unsigned IsCMP(unsigned Op) {
168 switch (Op) {
169 default:
170 return false;
171 case M68k::CMP8dd:
172 case M68k::CMP8df:
173 case M68k::CMP8di:
174 case M68k::CMP8dj:
175 case M68k::CMP8dp:
176 case M68k::CMP16dr:
177 case M68k::CMP16df:
178 case M68k::CMP16di:
179 case M68k::CMP16dj:
180 case M68k::CMP16dp:
181 return true;
182 }
183}
184
185static inline bool IsSETCC(unsigned SETCC) {
186 switch (SETCC) {
187 default:
188 return false;
189 case M68k::SETd8eq:
190 case M68k::SETd8ne:
191 case M68k::SETd8lt:
192 case M68k::SETd8ge:
193 case M68k::SETd8le:
194 case M68k::SETd8gt:
195 case M68k::SETd8cs:
196 case M68k::SETd8cc:
197 case M68k::SETd8ls:
198 case M68k::SETd8hi:
199 case M68k::SETd8pl:
200 case M68k::SETd8mi:
201 case M68k::SETd8vc:
202 case M68k::SETd8vs:
203 case M68k::SETj8eq:
204 case M68k::SETj8ne:
205 case M68k::SETj8lt:
206 case M68k::SETj8ge:
207 case M68k::SETj8le:
208 case M68k::SETj8gt:
209 case M68k::SETj8cs:
210 case M68k::SETj8cc:
211 case M68k::SETj8ls:
212 case M68k::SETj8hi:
213 case M68k::SETj8pl:
214 case M68k::SETj8mi:
215 case M68k::SETj8vc:
216 case M68k::SETj8vs:
217 case M68k::SETp8eq:
218 case M68k::SETp8ne:
219 case M68k::SETp8lt:
220 case M68k::SETp8ge:
221 case M68k::SETp8le:
222 case M68k::SETp8gt:
223 case M68k::SETp8cs:
224 case M68k::SETp8cc:
225 case M68k::SETp8ls:
226 case M68k::SETp8hi:
227 case M68k::SETp8pl:
228 case M68k::SETp8mi:
229 case M68k::SETp8vc:
230 case M68k::SETp8vs:
231 return true;
232 }
233}
234
235}
236
238 virtual void anchor();
239
240protected:
243
244public:
246
248
249
250
251
253
257 bool AllowModify) const override;
258
262 bool AllowModify) const;
263
265 int *BytesRemoved = nullptr) const override;
266
270 int *BytesAdded = nullptr) const override;
271
274 bool KillSrc, bool RenamableDest = false,
275 bool RenamableSrc = false) const override;
276
280
285
290
292
294
295
298
299
302
303
305
306
308
309
311 MVT MVTSrc) const;
312
313
316
317
319 bool IsPush) const;
320
321
323
324
326 bool IsRM) const;
327
328
329
330
332
333 std::pair<unsigned, unsigned>
335
338};
339
340}
341
342#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file contains small standalone helper functions and enum definitions for the M68k target useful ...
This file contains the M68k implementation of the TargetRegisterInfo class.
This file contains the entry points for global functions defined in the M68k target library,...
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned getGlobalBaseReg(MachineFunction *MF) const
Return a virtual register initialized with the global base register value.
const M68kSubtarget & Subtarget
Definition M68kInstrInfo.h:241
bool ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const
Move immediate to register.
bool ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned, MVT MVTDst, MVT MVTSrc) const
Move from register and extend.
const M68kRegisterInfo & getRegisterInfo() const
TargetInstrInfo is a superset of MRegister info.
Definition M68kInstrInfo.h:252
const M68kRegisterInfo RI
Definition M68kInstrInfo.h:242
static const M68kInstrInfo * create(M68kSubtarget &STI)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const override
bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const
Move across register classes without extension.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsRM) const
Expand all MOVEM pseudos into real MOVEMs.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsPush) const
Push/Pop to/from stack.
M68kInstrInfo(const M68kSubtarget &STI)
void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const
Add appropriate ZExt nodes.
bool ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const
Moves to/from CCR.
bool ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned, const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const
Move from memory and extend.
bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const override
void AddSExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const
Add appropriate SExt nodes.
Describe properties that are true of each instruction in the target description file.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool IsSETCC(unsigned SETCC)
Definition M68kInstrInfo.h:185
static unsigned IsCMP(unsigned Op)
Definition M68kInstrInfo.h:167
CondCode
Definition M68kInstrInfo.h:34
@ COND_T
Definition M68kInstrInfo.h:35
@ COND_LE
Definition M68kInstrInfo.h:50
@ COND_MI
Definition M68kInstrInfo.h:46
@ COND_F
Definition M68kInstrInfo.h:36
@ COND_VC
Definition M68kInstrInfo.h:43
@ COND_INVALID
Definition M68kInstrInfo.h:52
@ LAST_VALID_COND
Definition M68kInstrInfo.h:51
@ COND_CC
Definition M68kInstrInfo.h:39
@ COND_VS
Definition M68kInstrInfo.h:44
@ COND_LT
Definition M68kInstrInfo.h:48
@ COND_GT
Definition M68kInstrInfo.h:49
@ COND_CS
Definition M68kInstrInfo.h:40
@ COND_NE
Definition M68kInstrInfo.h:41
@ COND_HI
Definition M68kInstrInfo.h:37
@ COND_EQ
Definition M68kInstrInfo.h:42
@ COND_PL
Definition M68kInstrInfo.h:45
@ COND_LS
Definition M68kInstrInfo.h:38
@ COND_GE
Definition M68kInstrInfo.h:47
static unsigned GetCondBranchFromCond(M68k::CondCode CC)
Definition M68kInstrInfo.h:97
static M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC)
Definition M68kInstrInfo.h:58
static M68k::CondCode GetCondFromBranchOpc(unsigned Opcode)
Definition M68kInstrInfo.h:132
This is an optimization pass for GlobalISel generic memory operations.
DWARFExpression::Operation Op