LLVM: lib/MCA/Context.cpp Source File (original) (raw)

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28namespace llvm {

29namespace mca {

30

31std::unique_ptr

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40 auto RCU = std::make_unique(SM);

41 auto PRF = std::make_unique(SM, MRI, Opts.RegisterFileSize);

42 auto LSU = std::make_unique(SM, Opts.LoadQueueSize,

44 auto HWS = std::make_unique(SM, *LSU);

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47 auto Fetch = std::make_unique(SrcMgr);

48 auto Dispatch =

49 std::make_unique(STI, MRI, Opts.DispatchWidth, *RCU, *PRF);

52 auto Retire = std::make_unique(*RCU, *PRF, *LSU);

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61 auto StagePipeline = std::make_unique();

62 StagePipeline->appendStage(std::move(Fetch));

64 StagePipeline->appendStage(std::make_unique(

66 StagePipeline->appendStage(std::move(Dispatch));

67 StagePipeline->appendStage(std::move(Execute));

68 StagePipeline->appendStage(std::move(Retire));

69 return StagePipeline;

70}

71

72std::unique_ptr

76 auto PRF = std::make_unique(SM, MRI, Opts.RegisterFileSize);

77 auto LSU = std::make_unique(SM, Opts.LoadQueueSize,

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81 auto Entry = std::make_unique(SrcMgr);

82 auto InOrderIssue = std::make_unique(STI, *PRF, CB, *LSU);

83 auto StagePipeline = std::make_unique();

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90 StagePipeline->appendStage(std::move(Entry));

91 StagePipeline->appendStage(std::move(InOrderIssue));

92 return StagePipeline;

93}

94

95}

96}

This file models the dispatch component of an instruction pipeline.

This file defines the Entry stage of an instruction pipeline.

This file defines the execution stage of a default instruction pipeline.

InOrderIssueStage implements an in-order execution pipeline.

This file defines a class for holding ownership of various simulated hardware units.

A scheduler for Processor Resource Units and Processor Resource Groups.

This file defines a stage that implements a queue of micro opcodes.

static bool Execute(ProcessInfo &PI, StringRef Program, ArrayRef< StringRef > Args, std::optional< ArrayRef< StringRef > > Env, ArrayRef< std::optional< StringRef > > Redirects, unsigned MemoryLimit, std::string *ErrMsg, BitVector *AffinityMask, bool DetachProcess)

This file defines a register mapping file class.

This file simulates the hardware responsible for retiring instructions.

This file defines the retire stage of a default instruction pipeline.

LLVM_ABI std::unique_ptr< Pipeline > createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)

Construct a basic pipeline for simulating an in-order pipeline.

Definition Context.cpp:73

void addHardwareUnit(std::unique_ptr< HardwareUnit > H)

LLVM_ABI std::unique_ptr< Pipeline > createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, CustomBehaviour &CB)

Construct a basic pipeline for simulating an out-of-order pipeline.

Definition Context.cpp:32

Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...

This is an optimization pass for GlobalISel generic memory operations.

Machine model for scheduling, bundling, and heuristics.

bool isOutOfOrder() const

Return true if machine supports out of order execution.

This is a convenience struct to hold the parameters necessary for creating the pre-built "default" ou...

unsigned MicroOpQueueSize

unsigned RegisterFileSize

bool EnableBottleneckAnalysis

unsigned DecodersThroughput

Abstracting the input code sequence (a sequence of MCInst) and assigning unique identifiers to every ...