Instruction.cpp Source File (original) (raw)

18namespace llvm {

19namespace mca {

22 unsigned Cycles) {

23 CRD.IID = IID;

24 CRD.RegID = RegID;

25 CRD.Cycles = Cycles;

26 DependentWriteCyclesLeft = Cycles;

27 DependentWrite = nullptr;

28}

31 unsigned Cycles) {

32 assert(DependentWrites);

40 --DependentWrites;

41 if (TotalCycles < Cycles) {

42 CRD.IID = IID;

43 CRD.RegID = RegID;

44 CRD.Cycles = Cycles;

45 TotalCycles = Cycles;

46 }

48 if (!DependentWrites) {

49 CyclesLeft = TotalCycles;

50 IsReady = !CyclesLeft;

51 }

52}

61 for (const std::pair<ReadState *, int> &User : Users) {

63 unsigned ReadCycles = std::max(0, CyclesLeft - User.second);

64 RS->writeStartEvent(IID, RegisterID, ReadCycles);

65 }

68 if (PartialWrite)

69 PartialWrite->writeStartEvent(IID, RegisterID, CyclesLeft);

70}

77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance);

78 User->writeStartEvent(IID, RegisterID, ReadCycles);

79 return;

80 }

82 Users.emplace_back(User, ReadAdvance);

83}

87 User->writeStartEvent(IID, RegisterID, std::max(0, CyclesLeft));

88 return;

89 }

91 assert(!PartialWrite && "PartialWrite already set!");

92 PartialWrite = User;

93 User->setDependentWrite(this);

94}

101 CyclesLeft--;

102

103 if (DependentWriteCyclesLeft)

104 DependentWriteCyclesLeft--;

105}

106

108

109 if (DependentWrites && TotalCycles) {

110 --TotalCycles;

111 return;

112 }

113

114

116 return;

117

118 if (CyclesLeft) {

119 --CyclesLeft;

120 IsReady = !CyclesLeft;

121 }

122}

123

124#ifndef NDEBUG

126 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID "

128}

129#endif

130

131#ifndef NDEBUG

133 dbgs() << "{ OpIdx=" << RD->OpIndex << ", RegID " << getRegisterID()

134 << ", Cycles Left=" << CyclesLeft << " }";

135}

136#endif

137

139 if (CriticalRegDep.Cycles)

140 return CriticalRegDep;

141

142 unsigned MaxLatency = 0;

145 if (WriteCRD.Cycles > MaxLatency)

146 CriticalRegDep = WriteCRD;

147 }

148

151 if (ReadCRD.Cycles > MaxLatency)

152 CriticalRegDep = ReadCRD;

153 }

154

155 return CriticalRegDep;

156}

157

159

160

161 Stage = IS_INVALID;

164 RCUTokenID = 0;

165 LSUTokenID = 0;

166 CriticalResourceMask = 0;

167 IsEliminated = false;

168}

169

171 assert(Stage == IS_INVALID);

172 Stage = IS_DISPATCHED;

173 RCUTokenID = RCUToken;

174

175

178}

179

181 assert(Stage == IS_READY);

182 Stage = IS_EXECUTING;

183

184

186

188 WS.onInstructionIssued(IID);

189

190

191 if (!CyclesLeft)

192 Stage = IS_EXECUTED;

193}

194

196 assert(Stage == IS_READY && "Invalid internal state!");

197 CyclesLeft = 0;

198 Stage = IS_EXECUTED;

199}

200

202 assert(isPending() && "Unexpected instruction stage found!");

203

205 return false;

206

207

209 return false;

210

211 Stage = IS_READY;

212 return true;

213}

214

217

219 return Use.isPending() || Use.isReady();

220 }))

221 return false;

222

223

225 [](const WriteState &Def) { return !Def.getDependentWrite(); }))

226 return false;

227

228 Stage = IS_PENDING;

229 return true;

230}

231

238

241 return;

242

245 Use.cycleEvent();

246

248 Def.cycleEvent();

249

251 return;

252 }

253

255 assert(CyclesLeft && "Instruction already executed?");

257 Def.cycleEvent();

258 CyclesLeft--;

259 if (!CyclesLeft)

260 Stage = IS_EXECUTED;

261}

262

263}

264}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file defines abstractions used by the Pipeline to model register reads, register writes and inst...

A Use represents the edge between a Value definition and its users.

SmallVectorImpl< WriteState > & getDefs()

unsigned getLatency() const

void clearOptimizableMove()

SmallVectorImpl< ReadState > & getUses()

LLVM_ABI void cycleEvent()

Definition Instruction.cpp:239

bool isDispatched() const

LLVM_ABI bool updateDispatched()

Definition Instruction.cpp:215

LLVM_ABI void forceExecuted()

Definition Instruction.cpp:195

LLVM_ABI const CriticalDependency & computeCriticalRegDep()

Definition Instruction.cpp:138

LLVM_ABI void execute(unsigned IID)

Definition Instruction.cpp:180

LLVM_ABI bool updatePending()

Definition Instruction.cpp:201

LLVM_ABI void dispatch(unsigned RCUTokenID)

Definition Instruction.cpp:170

LLVM_ABI void update()

Definition Instruction.cpp:232

LLVM_ABI void reset()

Definition Instruction.cpp:158

Tracks register operand latency in cycles.

LLVM_ABI void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)

Definition Instruction.cpp:30

LLVM_ABI void cycleEvent()

Definition Instruction.cpp:107

MCPhysReg getRegisterID() const

void dump() const

Definition Instruction.cpp:132

Tracks uses of a register definition (e.g.

LLVM_ABI void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)

Definition Instruction.cpp:21

unsigned getLatency() const

int getCyclesLeft() const

void dump() const

Definition Instruction.cpp:125

LLVM_ABI void cycleEvent()

Definition Instruction.cpp:96

WriteState(const WriteDescriptor &Desc, MCPhysReg RegID, bool clearsSuperRegs=false, bool writesZero=false)

LLVM_ABI void onInstructionIssued(unsigned IID)

Definition Instruction.cpp:54

MCPhysReg getRegisterID() const

LLVM_ABI void addUser(unsigned IID, ReadState *Use, int ReadAdvance)

Definition Instruction.cpp:72

constexpr int UNKNOWN_CYCLES

This is an optimization pass for GlobalISel generic memory operations.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

A critical data dependency descriptor.