Instruction.h Source File (original) (raw)

15#ifndef LLVM_MCA_INSTRUCTION_H

16#define LLVM_MCA_INSTRUCTION_H

25#ifndef NDEBUG

27#endif

29namespace llvm {

31namespace mca {

41 enum MCAOperandType : unsigned char {

42 kInvalid,

43 kRegister,

44 kImmediate,

45 kSFPImmediate,

46 kDFPImmediate,

47 };

48 MCAOperandType Kind;

50 union {

55 };

61 unsigned Index;

63public:

66 bool isValid() const { return Kind != kInvalid; }

67 bool isReg() const { return Kind == kRegister; }

68 bool isImm() const { return Kind == kImmediate; }

69 bool isSFPImm() const { return Kind == kSFPImmediate; }

70 bool isDFPImm() const { return Kind == kDFPImmediate; }

74 assert(isReg() && "This is not a register operand!");

76 }

93 void setIndex(const unsigned Idx) { Index = Idx; }

95 unsigned getIndex() const { return Index; }

99 Op.Kind = kRegister;

101 return Op;

102 }

103

106 Op.Kind = kImmediate;

107 Op.ImmVal = Val;

108 return Op;

109 }

110

113 Op.Kind = kSFPImmediate;

114 Op.SFPImmVal = Val;

115 return Op;

116 }

117

120 Op.Kind = kDFPImmediate;

121 Op.FPImmVal = Val;

122 return Op;

123 }

124

127 Op.Kind = kInvalid;

128 Op.FPImmVal = 0;

129 return Op;

130 }

131};

132

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159};

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177};

178

179class ReadState;

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201 int CyclesLeft;

202

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209

210 unsigned PRFID;

211

212

213

214 bool ClearsSuperRegs;

215

216

217 bool WritesZero;

218

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223 bool IsEliminated;

224

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231

233 unsigned DependentWriteCyclesLeft;

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246public:

248 bool clearsSuperRegs = false, bool writesZero = false)

249 : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0),

250 ClearsSuperRegs(clearsSuperRegs), WritesZero(writesZero),

251 IsEliminated(false), DependentWrite(nullptr), PartialWrite(nullptr),

252 DependentWriteCyclesLeft(0), CRD() {}

253

256

262 unsigned getLatency() const { return WD->Latency; }

264 return DependentWriteCyclesLeft;

265 }

268

269

270

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275

276

278

280 unsigned NumUsers = Users.size();

281 if (PartialWrite)

282 ++NumUsers;

283 return NumUsers;

284 }

285

289

291 if (DependentWrite)

292 return false;

294 return !CyclesLeft || CyclesLeft < getLatency();

295 }

296

300

305 assert(Users.empty() && "Write is in an inconsistent state.");

306 CyclesLeft = 0;

307 IsEliminated = true;

308 }

309

310 void setPRF(unsigned PRF) { PRFID = PRF; }

311

312

315

316#ifndef NDEBUG

317 void dump() const;

318#endif

319};

320

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329

330 unsigned PRFID;

331

332

333

334 unsigned DependentWrites;

335

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337

338

339 int CyclesLeft;

340

341

342

343 unsigned TotalCycles;

344

346

347

348 bool IsReady;

349

350 bool IsZero;

351

352 bool IndependentFromDef;

353

354public:

356 : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0),

358 IsZero(false), IndependentFromDef(false) {}

359

365

366 bool isPending() const { return !IndependentFromDef && CyclesLeft > 0; }

367 bool isReady() const { return IsReady; }

369

372

376 DependentWrites = Writes;

377 IsReady = !Writes;

378 }

379

383

384#ifndef NDEBUG

385 void dump() const;

386#endif

387};

388

389

390

391

393 unsigned Begin;

394 unsigned End;

395 bool Reserved;

396

397public:

398 CycleSegment(unsigned StartCycle, unsigned EndCycle, bool IsReserved = false)

399 : Begin(StartCycle), End(EndCycle), Reserved(IsReserved) {}

400

407 bool isExecuting() const { return Begin == 0 && End != 0; }

410 return Begin < Other.Begin;

411 }

413 if (Begin)

414 Begin--;

415 if (End)

416 End--;

417 return *this;

418 }

419

420 bool isValid() const { return Begin <= End; }

421 unsigned size() const { return End - Begin; };

423 assert(End >= Cycles);

424 End -= Cycles;

425 }

426

427 unsigned begin() const { return Begin; }

428 unsigned end() const { return End; }

429 void setEnd(unsigned NewEnd) { End = NewEnd; }

432};

433

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444 unsigned size() const { return CS.size(); }

447};

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493};

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505 bool IsOptimizableMove;

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516 std::vector Operands;

517

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519 unsigned Opcode;

520

521

522 bool IsALoadBarrier : 1;

523 bool IsAStoreBarrier : 1;

524

525

526 bool MayLoad : 1;

527 bool MayStore : 1;

528 bool HasSideEffects : 1;

529 bool BeginGroup : 1;

530 bool EndGroup : 1;

531 bool RetireOOO : 1;

532

533public:

535 : Desc(D), IsOptimizableMove(false), Operands(0), Opcode(Opcode),

536 IsALoadBarrier(false), IsAStoreBarrier(false) {}

537

543

544 unsigned getLatency() const { return Desc.MaxLatency; }

546 unsigned getOpcode() const { return Opcode; }

549 void setLoadBarrier(bool IsBarrier) { IsALoadBarrier = IsBarrier; }

550 void setStoreBarrier(bool IsBarrier) { IsAStoreBarrier = IsBarrier; }

551

552

553

556 return Op.getIndex() == Idx;

557 });

558 if (It == Operands.end())

559 return nullptr;

560 return &(*It);

561 }

564

567 [](const WriteState &Def) { return Def.getNumUsers() > 0; });

568 }

569

571 unsigned NumUsers = 0;

573 NumUsers += Def.getNumUsers();

574 return NumUsers;

575 }

576

577

581 bool isMemOp() const { return MayLoad || MayStore; }

582

583

584 void setMayLoad(bool newVal) { MayLoad = newVal; }

590

597};

598

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602

604 enum InstrStage {

605 IS_INVALID,

606 IS_DISPATCHED,

607 IS_PENDING,

608 IS_READY,

609 IS_EXECUTING,

610 IS_EXECUTED,

611 IS_RETIRED

612 };

613

614

615 enum InstrStage Stage;

616

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619 int CyclesLeft;

620

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622 unsigned RCUTokenID;

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627 unsigned LSUTokenID;

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644 uint64_t CriticalResourceMask;

645

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647 bool IsEliminated;

648

649public:

652 CyclesLeft(UNKNOWN_CYCLES), RCUTokenID(0), LSUTokenID(0),

653 UsedBuffers(D.UsedBuffers), CriticalRegDep(), CriticalMemDep(),

654 CriticalResourceMask(0), IsEliminated(false) {}

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687 bool isInvalid() const { return Stage == IS_INVALID; }

688 bool isDispatched() const { return Stage == IS_DISPATCHED; }

689 bool isPending() const { return Stage == IS_PENDING; }

690 bool isReady() const { return Stage == IS_READY; }

691 bool isExecuting() const { return Stage == IS_EXECUTING; }

692 bool isExecuted() const { return Stage == IS_EXECUTED; }

693 bool isRetired() const { return Stage == IS_RETIRED; }

695

696

699

701 assert(isExecuted() && "Instruction is in an invalid state!");

702 Stage = IS_RETIRED;

703 }

704

709 CriticalMemDep = MemDep;

710 }

711

714 CriticalResourceMask = ResourceMask;

715 }

716

718};

719

720

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722

724 std::pair<unsigned, Instruction *> Data;

725

726public:

729

733 return Data.first < Other.Data.first;

734 }

735

739

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741 explicit operator bool() const { return Data.second != nullptr; }

742

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745

746#ifndef NDEBUG

748#endif

749};

750

751#ifndef NDEBUG

753 IR.print(OS);

754 return OS;

755}

756#endif

757

758}

759}

760

761#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

Legalize the Machine IR a function s Machine IR

This file defines the SmallVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

A Use represents the edge between a Value definition and its users.

A sequence of cycles.

Definition Instruction.h:392

CycleSegment(unsigned StartCycle, unsigned EndCycle, bool IsReserved=false)

Definition Instruction.h:398

bool isExecuting() const

Definition Instruction.h:407

void setReserved()

Definition Instruction.h:431

bool operator<(const CycleSegment &Other) const

Definition Instruction.h:409

bool startsAfter(const CycleSegment &CS) const

Definition Instruction.h:402

bool contains(unsigned Cycle) const

Definition Instruction.h:401

void setEnd(unsigned NewEnd)

Definition Instruction.h:429

void subtract(unsigned Cycles)

Definition Instruction.h:422

CycleSegment & operator--()

Definition Instruction.h:412

unsigned end() const

Definition Instruction.h:428

bool isReserved() const

Definition Instruction.h:430

unsigned size() const

Definition Instruction.h:421

bool endsBefore(const CycleSegment &CS) const

Definition Instruction.h:403

bool isExecuted() const

Definition Instruction.h:408

bool isValid() const

Definition Instruction.h:420

unsigned begin() const

Definition Instruction.h:427

bool overlaps(const CycleSegment &CS) const

Definition Instruction.h:404

An InstRef contains both a SourceMgr index and Instruction pair.

Definition Instruction.h:723

void invalidate()

Invalidate this reference.

Definition Instruction.h:744

bool operator<(const InstRef &Other) const

Definition Instruction.h:732

InstRef()

Definition Instruction.h:727

const Instruction * getInstruction() const

Definition Instruction.h:738

InstRef(unsigned Index, Instruction *I)

Definition Instruction.h:728

Instruction * getInstruction()

Definition Instruction.h:737

unsigned getSourceIndex() const

Definition Instruction.h:736

bool operator!=(const InstRef &Other) const

Definition Instruction.h:731

bool operator==(const InstRef &Other) const

Definition Instruction.h:730

void print(raw_ostream &OS) const

Definition Instruction.h:747

void setEndGroup(bool newVal)

Definition Instruction.h:588

unsigned getOpcode() const

Definition Instruction.h:546

bool isAStoreBarrier() const

Definition Instruction.h:548

bool isOptimizableMove() const

Definition Instruction.h:578

void setRetireOOO(bool newVal)

Definition Instruction.h:589

bool getRetireOOO() const

Definition Instruction.h:596

ArrayRef< WriteState > getDefs() const

Definition Instruction.h:539

void addOperand(const MCAOperand Op)

Definition Instruction.h:563

unsigned getNumMicroOps() const

Definition Instruction.h:545

const InstrDesc & getDesc() const

Definition Instruction.h:542

const MCAOperand * getOperand(const unsigned Idx) const

Return the MCAOperand which corresponds to index Idx within the original MCInst.

Definition Instruction.h:554

SmallVectorImpl< WriteState > & getDefs()

Definition Instruction.h:538

bool hasDependentUsers() const

Definition Instruction.h:565

unsigned getLatency() const

Definition Instruction.h:544

void clearOptimizableMove()

Definition Instruction.h:580

void setBeginGroup(bool newVal)

Definition Instruction.h:587

bool getHasSideEffects() const

Definition Instruction.h:593

bool getMayStore() const

Definition Instruction.h:592

bool isMemOp() const

Definition Instruction.h:581

bool getMayLoad() const

Definition Instruction.h:591

SmallVectorImpl< ReadState > & getUses()

Definition Instruction.h:540

void setLoadBarrier(bool IsBarrier)

Definition Instruction.h:549

unsigned getNumOperands() const

Definition Instruction.h:562

bool getBeginGroup() const

Definition Instruction.h:594

void setStoreBarrier(bool IsBarrier)

Definition Instruction.h:550

void setHasSideEffects(bool newVal)

Definition Instruction.h:586

void setMayStore(bool newVal)

Definition Instruction.h:585

ArrayRef< ReadState > getUses() const

Definition Instruction.h:541

InstructionBase(const InstrDesc &D, const unsigned Opcode)

Definition Instruction.h:534

unsigned getNumUsers() const

Definition Instruction.h:570

void setOptimizableMove()

Definition Instruction.h:579

bool getEndGroup() const

Definition Instruction.h:595

bool isALoadBarrier() const

Definition Instruction.h:547

void setMayLoad(bool newVal)

Definition Instruction.h:584

An instruction propagated through the simulated instruction pipeline.

Definition Instruction.h:603

LLVM_ABI void cycleEvent()

bool isDispatched() const

Definition Instruction.h:688

bool isEliminated() const

Definition Instruction.h:694

Instruction(const InstrDesc &D, const unsigned Opcode)

Definition Instruction.h:650

bool isExecuted() const

Definition Instruction.h:692

uint64_t getCriticalResourceMask() const

Definition Instruction.h:712

unsigned getRCUTokenID() const

Definition Instruction.h:658

LLVM_ABI bool updateDispatched()

const CriticalDependency & getCriticalMemDep() const

Definition Instruction.h:706

const CriticalDependency & getCriticalRegDep() const

Definition Instruction.h:705

bool isExecuting() const

Definition Instruction.h:691

LLVM_ABI void forceExecuted()

int getCyclesLeft() const

Definition Instruction.h:666

bool isRetired() const

Definition Instruction.h:693

void setCriticalResourceMask(uint64_t ResourceMask)

Definition Instruction.h:713

bool isReady() const

Definition Instruction.h:690

LLVM_ABI const CriticalDependency & computeCriticalRegDep()

LLVM_ABI void execute(unsigned IID)

bool isInvalid() const

Definition Instruction.h:687

LLVM_ABI bool updatePending()

void setLSUTokenID(unsigned LSUTok)

Definition Instruction.h:660

void setEliminated()

Definition Instruction.h:698

void setUsedBuffers(uint64_t Mask)

Definition Instruction.h:663

void setCriticalMemDep(const CriticalDependency &MemDep)

Definition Instruction.h:708

LLVM_ABI void dispatch(unsigned RCUTokenID)

void clearUsedBuffers()

Definition Instruction.h:664

uint64_t getUsedBuffers() const

Definition Instruction.h:662

void retire()

Definition Instruction.h:700

bool isPending() const

Definition Instruction.h:689

unsigned getLSUTokenID() const

Definition Instruction.h:659

A representation of an mca::Instruction operand for use in mca::CustomBehaviour.

Definition Instruction.h:37

unsigned RegVal

Definition Instruction.h:51

uint64_t FPImmVal

Definition Instruction.h:54

unsigned getReg() const

Returns the register number.

Definition Instruction.h:73

static MCAOperand createSFPImm(uint32_t Val)

Definition Instruction.h:111

uint32_t getSFPImm() const

Definition Instruction.h:83

MCAOperand()

Definition Instruction.h:64

static MCAOperand createInvalid()

Definition Instruction.h:125

static MCAOperand createDFPImm(uint64_t Val)

Definition Instruction.h:118

static MCAOperand createImm(int64_t Val)

Definition Instruction.h:104

static MCAOperand createReg(unsigned Reg)

Definition Instruction.h:97

int64_t ImmVal

Definition Instruction.h:52

unsigned getIndex() const

Definition Instruction.h:95

uint32_t SFPImmVal

Definition Instruction.h:53

bool isImm() const

Definition Instruction.h:68

bool isDFPImm() const

Definition Instruction.h:70

bool isSFPImm() const

Definition Instruction.h:69

int64_t getImm() const

Definition Instruction.h:78

uint64_t getDFPImm() const

Definition Instruction.h:88

void setIndex(const unsigned Idx)

Definition Instruction.h:93

bool isReg() const

Definition Instruction.h:67

bool isValid() const

Definition Instruction.h:66

Tracks register operand latency in cycles.

Definition Instruction.h:325

unsigned getRegisterFileID() const

Definition Instruction.h:363

unsigned getSchedClass() const

Definition Instruction.h:361

LLVM_ABI void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)

bool isIndependentFromDef() const

Definition Instruction.h:370

const ReadDescriptor & getDescriptor() const

Definition Instruction.h:360

void setPRF(unsigned ID)

Definition Instruction.h:382

const CriticalDependency & getCriticalRegDep() const

Definition Instruction.h:364

LLVM_ABI void cycleEvent()

void setDependentWrites(unsigned Writes)

Definition Instruction.h:375

bool isReady() const

Definition Instruction.h:367

MCPhysReg getRegisterID() const

Definition Instruction.h:362

bool isImplicitRead() const

Definition Instruction.h:368

ReadState(const ReadDescriptor &Desc, MCPhysReg RegID)

Definition Instruction.h:355

void setReadZero()

Definition Instruction.h:381

void setIndependentFromDef()

Definition Instruction.h:371

bool isPending() const

Definition Instruction.h:366

bool isReadZero() const

Definition Instruction.h:380

Tracks uses of a register definition (e.g.

Definition Instruction.h:196

unsigned getRegisterFileID() const

Definition Instruction.h:261

bool isEliminated() const

Definition Instruction.h:288

const WriteState * getDependentWrite() const

Definition Instruction.h:266

LLVM_ABI void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles)

unsigned getDependentWriteCyclesLeft() const

Definition Instruction.h:263

void setWriteZero()

Definition Instruction.h:303

void setRegisterID(const MCPhysReg RegID)

Definition Instruction.h:260

unsigned getLatency() const

Definition Instruction.h:262

WriteState & operator=(const WriteState &Other)=default

void setPRF(unsigned PRF)

Definition Instruction.h:310

void setDependentWrite(const WriteState *Other)

Definition Instruction.h:301

int getCyclesLeft() const

Definition Instruction.h:257

void setEliminated()

Definition Instruction.h:304

LLVM_ABI void cycleEvent()

WriteState(const WriteDescriptor &Desc, MCPhysReg RegID, bool clearsSuperRegs=false, bool writesZero=false)

Definition Instruction.h:247

const CriticalDependency & getCriticalRegDep() const

Definition Instruction.h:267

LLVM_ABI void onInstructionIssued(unsigned IID)

WriteState(const WriteState &Other)=default

bool clearsSuperRegisters() const

Definition Instruction.h:286

unsigned getNumUsers() const

Definition Instruction.h:279

MCPhysReg getRegisterID() const

Definition Instruction.h:259

bool isWriteZero() const

Definition Instruction.h:287

bool isExecuted() const

Definition Instruction.h:297

unsigned getWriteResourceID() const

Definition Instruction.h:258

LLVM_ABI void addUser(unsigned IID, ReadState *Use, int ReadAdvance)

bool isReady() const

Definition Instruction.h:290

This class implements an extremely fast bulk output stream that can only output to a stream.

char InstructionError< T >::ID

raw_ostream & operator<<(raw_ostream &OS, const InstRef &IR)

Definition Instruction.h:752

constexpr int UNKNOWN_CYCLES

Definition Instruction.h:33

This is an optimization pass for GlobalISel generic memory operations.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

Implement std::hash so that hash_code can be used in STL containers.

A critical data dependency descriptor.

Definition Instruction.h:184

unsigned IID

Definition Instruction.h:185

MCPhysReg RegID

Definition Instruction.h:186

unsigned Cycles

Definition Instruction.h:187

An instruction descriptor.

Definition Instruction.h:450

uint64_t UsedProcResGroups

Definition Instruction.h:465

uint64_t UsedProcResUnits

Definition Instruction.h:462

SmallVector< WriteDescriptor, 2 > Writes

Definition Instruction.h:451

InstrDesc(const InstrDesc &Other)=delete

unsigned IsRecyclable

Definition Instruction.h:482

SmallVector< std::pair< uint64_t, ResourceUsage >, 4 > Resources

Definition Instruction.h:456

uint64_t UsedBuffers

Definition Instruction.h:459

unsigned HasPartiallyOverlappingGroups

Definition Instruction.h:485

SmallVector< ReadDescriptor, 4 > Reads

Definition Instruction.h:452

bool isZeroLatency() const

Definition Instruction.h:488

unsigned MaxLatency

Definition Instruction.h:467

InstrDesc & operator=(const InstrDesc &Other)=delete

unsigned MustIssueImmediately

Definition Instruction.h:477

unsigned NumMicroOps

Definition Instruction.h:469

unsigned SchedClassID

Definition Instruction.h:473

A register read descriptor.

Definition Instruction.h:162

unsigned SchedClassID

Definition Instruction.h:174

bool isImplicitRead() const

Definition Instruction.h:176

MCPhysReg RegisterID

Definition Instruction.h:171

int OpIndex

Definition Instruction.h:166

unsigned UseIndex

Definition Instruction.h:169

unsigned NumUnits

Definition Instruction.h:441

CycleSegment CS

Definition Instruction.h:440

void setReserved()

Definition Instruction.h:446

ResourceUsage(CycleSegment Cycles, unsigned Units=1)

Definition Instruction.h:442

unsigned size() const

Definition Instruction.h:444

bool isReserved() const

Definition Instruction.h:445

A register write descriptor.

Definition Instruction.h:134

unsigned SClassOrWriteResourceID

Definition Instruction.h:152

bool IsOptionalDef

Definition Instruction.h:156

MCPhysReg RegisterID

Definition Instruction.h:143

unsigned Latency

Definition Instruction.h:140

int OpIndex

Definition Instruction.h:138

bool isImplicitWrite() const

Definition Instruction.h:158