MCSchedule.cpp Source File (original) (raw)

18#include

19#include <type_traits>

21using namespace llvm;

23static_assert(std::is_trivial_v,

24 "MCSchedModel is required to be a trivial type");

26 DefaultMicroOpBufferSize,

27 DefaultLoopMicroOpBufferSize,

28 DefaultLoadLatency,

29 DefaultHighLatency,

30 DefaultMispredictPenalty,

31 false,

32 true,

33 false,

34 0,

35 nullptr,

36 nullptr,

37 0,

38 0,

39 nullptr,

40 nullptr,

41 nullptr};

47 DefIdx != DefEnd; ++DefIdx) {

52 if (WLEntry->Cycles < 0)

53 return WLEntry->Cycles;

55 }

57}

60 unsigned SchedClass) const {

63 return 0;

68}

72 const MCInst &Inst) const {

75 STI, MCII, Inst,

77 if (!SCDesc->isValid())

78 return nullptr;

81 unsigned SchedClass = 0;

82 while (SCDesc->isVariant()) {

83 SchedClass =

86 }

88 if (!SchedClass) {

89 assert(false && "unsupported variant scheduling class");

90 return nullptr;

91 }

93 return SCDesc;

94 });

95}

97double

100 std::optional MinThroughput;

104 for (; I != E; ++I) {

105 if (->ReleaseAtCycle || I->ReleaseAtCycle == I->AcquireAtCycle)

106 continue;

107 assert(I->ReleaseAtCycle > I->AcquireAtCycle && "invalid resource segment");

109 double Throughput =

110 double(NumUnits) / double(I->ReleaseAtCycle - I->AcquireAtCycle);

111 MinThroughput =

112 MinThroughput ? std::min(*MinThroughput, Throughput) : Throughput;

113 }

114 if (MinThroughput)

115 return 1.0 / *MinThroughput;

116

117

118

120}

121

122double

125 const MCInst &Inst) const {

128

129

130

133

138 }

139

140 if (SchedClass)

142

144}

145

146double

149 std::optional Throughput;

152 for (; I != E; ++I) {

153 if (->getCycles())

154 continue;

155 double Temp = llvm::popcount(I->getUnits()) * 1.0 / I->getCycles();

156 Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;

157 }

158 if (Throughput)

159 return 1.0 / *Throughput;

160

161

162

164}

165

166unsigned

168 unsigned WriteResourceID) {

169 if (Entries.empty())

170 return 0;

171

172 int DelayCycles = 0;

174 if (E.WriteResourceID != WriteResourceID)

175 continue;

176 DelayCycles = std::min(DelayCycles, E.Cycles);

177 }

178

179 return std::abs(DelayCycles);

180}

181

184

186 if (Entries.empty())

187 return 0;

188

189 unsigned MaxLatency = 0;

190 unsigned WriteResourceID = 0;

192

193 for (unsigned DefIdx = 0; DefIdx != DefEnd; ++DefIdx) {

194

197 unsigned Cycles = 0;

198

199 if (WLEntry->Cycles > 0)

201 if (Cycles > MaxLatency) {

202 MaxLatency = Cycles;

204 }

205 }

206

208 if (E.WriteResourceID == WriteResourceID)

209 return E.Cycles;

210 }

211

212

213 return 0;

214}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

bool empty() const

empty - Check if the array is empty.

const InstrStage * beginStage(unsigned ItinClassIndx) const

Return the first stage of the itinerary.

const InstrStage * endStage(unsigned ItinClassIndx) const

Return the last+1 stage of the itinerary.

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

unsigned getSchedClass() const

Return the scheduling class for this instruction.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Generic base class for all target subtargets.

const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const

virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const

Resolve a variant scheduling class for the given MCInst and CPU.

ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries(const MCSchedClassDesc &SC) const

Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.

const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const

const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const

Return an iterator at the first process resource consumed by the given scheduling class.

const MCSchedModel & getSchedModel() const

Get the machine model for this subtarget's CPU.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

constexpr int popcount(T Value) noexcept

Count the number of set bits in a value.

These values represent a non-pipelined step in the execution of an instruction.

Specify the number of cycles allowed after instruction issue before a particular use operand reads it...

Summarize the scheduling resources required for an instruction of a particular scheduling class.

uint16_t NumWriteLatencyEntries

Machine model for scheduling, bundling, and heuristics.

static LLVM_ABI const MCSchedModel Default

Returns the default initialized model.

static LLVM_ABI unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)

Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...

Definition MCSchedule.cpp:167

const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const

unsigned getProcessorID() const

static LLVM_ABI int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)

Returns the latency value for the scheduling class.

Definition MCSchedule.cpp:43

friend class InstrItineraryData

const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const

static LLVM_ABI unsigned getBypassDelayCycles(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)

Returns the bypass delay cycle for the maximum latency write cycle.

Definition MCSchedule.cpp:182

static LLVM_ABI double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)

Definition MCSchedule.cpp:98

static const unsigned DefaultIssueWidth

Specify the latency in cpu cycles for a particular scheduling class and def index.

Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...