MSP430InstrInfo.cpp Source File (original) (raw)

19using namespace llvm;

21#define GET_INSTRINFO_CTOR_DTOR

22#include "MSP430GenInstrInfo.inc"

25void MSP430InstrInfo::anchor() {}

28 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),

29 RI() {}

45 if (RC == &MSP430::GR16RegClass)

49 else if (RC == &MSP430::GR8RegClass)

53 else

54 llvm_unreachable("Cannot store this register to stack slot!");

55}

59 Register DestReg, int FrameIdx,

73 if (RC == &MSP430::GR16RegClass)

77 else if (RC == &MSP430::GR8RegClass)

81 else

82 llvm_unreachable("Cannot store this register to stack slot!");

83}

89 bool RenamableDest, bool RenamableSrc) const {

90 unsigned Opc;

91 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))

92 Opc = MSP430::MOV16rr;

93 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))

94 Opc = MSP430::MOV8rr;

95 else

100}

101

103 int *BytesRemoved) const {

104 assert(!BytesRemoved && "code size not handled");

105

107 unsigned Count = 0;

108

110 --I;

111 if (I->isDebugInstr())

112 continue;

113 if (I->getOpcode() != MSP430::JMP &&

114 I->getOpcode() != MSP430::JCC &&

115 I->getOpcode() != MSP430::Bi &&

116 I->getOpcode() != MSP430::Br &&

117 I->getOpcode() != MSP430::Bm)

118 break;

119

120 I->eraseFromParent();

122 ++Count;

123 }

124

125 return Count;

126}

127

130 assert(Cond.size() == 1 && "Invalid Xbranch condition!");

131

133

134 switch (CC) {

138 break;

141 break;

144 break;

147 break;

150 break;

153 break;

154 }

155

157 return false;

158}

159

164 bool AllowModify) const {

165

166

169 --I;

170 if (I->isDebugInstr())

171 continue;

172

173

174

175 if (!isUnpredicatedTerminator(*I))

176 break;

177

178

179

180 if (->isBranch())

181 return true;

182

183

184 if (I->getOpcode() == MSP430::Br ||

185 I->getOpcode() == MSP430::Bm)

186 return true;

187

188

189 if (I->getOpcode() == MSP430::JMP || I->getOpcode() == MSP430::Bi) {

190 if (!AllowModify) {

191 TBB = I->getOperand(0).getMBB();

192 continue;

193 }

194

195

197 Cond.clear();

198 FBB = nullptr;

199

200

202 TBB = nullptr;

203 I->eraseFromParent();

205 continue;

206 }

207

208

209 TBB = I->getOperand(0).getMBB();

210 continue;

211 }

212

213

214 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");

218 return true;

219

220

221 if (Cond.empty()) {

222 FBB = TBB;

223 TBB = I->getOperand(0).getMBB();

225 continue;

226 }

227

228

229

232

233

234

235 if (TBB != I->getOperand(0).getMBB())

236 return true;

237

239

240 if (OldBranchCode == BranchCode)

241 continue;

242

243 return true;

244 }

245

246 return false;

247}

248

254 int *BytesAdded) const {

255

256 assert(TBB && "insertBranch must not be told to insert a fallthrough");

258 "MSP430 branch conditions have one component!");

259 assert(!BytesAdded && "code size not handled");

260

261 if (Cond.empty()) {

262

263 assert(!FBB && "Unconditional branch with multiple successors!");

265 return 1;

266 }

267

268

269 unsigned Count = 0;

271 ++Count;

272

273 if (FBB) {

274

276 ++Count;

277 }

278 return Count;

279}

280

281

282

283

286

287 switch (Desc.getOpcode()) {

288 case TargetOpcode::CFI_INSTRUCTION:

289 case TargetOpcode::EH_LABEL:

290 case TargetOpcode::IMPLICIT_DEF:

291 case TargetOpcode::KILL:

292 case TargetOpcode::DBG_VALUE:

293 return 0;

294 case TargetOpcode::INLINEASM:

295 case TargetOpcode::INLINEASM_BR: {

300 }

301 }

302

303 return Desc.getSize();

304}

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override

Measure the specified inline asm to determine an approximation of its length.

Describe properties that are true of each instruction in the target description file.

Wrapper class representing physical registers. Should be passed by value.

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

MSP430InstrInfo(MSP430Subtarget &STI)

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

GetInstSize - Return the number of bytes of code the specified instruction may be.

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

bool isLayoutSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

static MachineOperand CreateImm(int64_t Val)

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

TargetInstrInfo - Interface to description of machine instruction set.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

unsigned getDefRegState(bool B)

unsigned getKillRegState(bool B)

Description of the encoding of one expression Op.

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.