MSP430InstrInfo.cpp Source File (original) (raw)

19using namespace llvm;

21#define GET_INSTRINFO_CTOR_DTOR

22#include "MSP430GenInstrInfo.inc"

25void MSP430InstrInfo::anchor() {}

28 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),

29 RI() {}

46 if (RC == &MSP430::GR16RegClass)

50 else if (RC == &MSP430::GR8RegClass)

54 else

55 llvm_unreachable("Cannot store this register to stack slot!");

56}

72 if (RC == &MSP430::GR16RegClass)

76 else if (RC == &MSP430::GR8RegClass)

80 else

81 llvm_unreachable("Cannot store this register to stack slot!");

82}

88 bool RenamableDest, bool RenamableSrc) const {

89 unsigned Opc;

90 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))

91 Opc = MSP430::MOV16rr;

92 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))

93 Opc = MSP430::MOV8rr;

94 else

99}

100

102 int *BytesRemoved) const {

103 assert(!BytesRemoved && "code size not handled");

104

106 unsigned Count = 0;

107

109 --I;

110 if (I->isDebugInstr())

111 continue;

112 if (I->getOpcode() != MSP430::JMP &&

113 I->getOpcode() != MSP430::JCC &&

114 I->getOpcode() != MSP430::Bi &&

115 I->getOpcode() != MSP430::Br &&

116 I->getOpcode() != MSP430::Bm)

117 break;

118

119 I->eraseFromParent();

121 ++Count;

122 }

123

124 return Count;

125}

126

129 assert(Cond.size() == 1 && "Invalid Xbranch condition!");

130

132

133 switch (CC) {

137 break;

140 break;

143 break;

146 break;

149 break;

152 break;

153 }

154

156 return false;

157}

158

163 bool AllowModify) const {

164

165

168 --I;

169 if (I->isDebugInstr())

170 continue;

171

172

173

174 if (!isUnpredicatedTerminator(*I))

175 break;

176

177

178

179 if (->isBranch())

180 return true;

181

182

183 if (I->getOpcode() == MSP430::Br ||

184 I->getOpcode() == MSP430::Bm)

185 return true;

186

187

188 if (I->getOpcode() == MSP430::JMP || I->getOpcode() == MSP430::Bi) {

189 if (!AllowModify) {

190 TBB = I->getOperand(0).getMBB();

191 continue;

192 }

193

194

196 Cond.clear();

197 FBB = nullptr;

198

199

201 TBB = nullptr;

202 I->eraseFromParent();

204 continue;

205 }

206

207

208 TBB = I->getOperand(0).getMBB();

209 continue;

210 }

211

212

213 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");

217 return true;

218

219

220 if (Cond.empty()) {

221 FBB = TBB;

222 TBB = I->getOperand(0).getMBB();

224 continue;

225 }

226

227

228

231

232

233

234 if (TBB != I->getOperand(0).getMBB())

235 return true;

236

238

239 if (OldBranchCode == BranchCode)

240 continue;

241

242 return true;

243 }

244

245 return false;

246}

247

253 int *BytesAdded) const {

254

255 assert(TBB && "insertBranch must not be told to insert a fallthrough");

257 "MSP430 branch conditions have one component!");

258 assert(!BytesAdded && "code size not handled");

259

260 if (Cond.empty()) {

261

262 assert(!FBB && "Unconditional branch with multiple successors!");

264 return 1;

265 }

266

267

268 unsigned Count = 0;

270 ++Count;

271

272 if (FBB) {

273

275 ++Count;

276 }

277 return Count;

278}

279

280

281

282

285

286 switch (Desc.getOpcode()) {

287 case TargetOpcode::CFI_INSTRUCTION:

288 case TargetOpcode::EH_LABEL:

289 case TargetOpcode::IMPLICIT_DEF:

290 case TargetOpcode::KILL:

291 case TargetOpcode::DBG_VALUE:

292 return 0;

293 case TargetOpcode::INLINEASM:

294 case TargetOpcode::INLINEASM_BR: {

299 }

300 }

301

302 return Desc.getSize();

303}

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override

Measure the specified inline asm to determine an approximation of its length.

Describe properties that are true of each instruction in the target description file.

Wrapper class representing physical registers. Should be passed by value.

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

MSP430InstrInfo(MSP430Subtarget &STI)

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

GetInstSize - Return the number of bytes of code the specified instruction may be.

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

bool isLayoutSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

static MachineOperand CreateImm(int64_t Val)

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

TargetInstrInfo - Interface to description of machine instruction set.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

unsigned getDefRegState(bool B)

unsigned getKillRegState(bool B)

Description of the encoding of one expression Op.

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.