MSP430InstrInfo.cpp Source File (original) (raw)

20using namespace llvm;

22#define GET_INSTRINFO_CTOR_DTOR

23#include "MSP430GenInstrInfo.inc"

26void MSP430InstrInfo::anchor() {}

30 MSP430::ADJCALLSTACKUP),

31 RI() {}

38 if (MI != MBB.end()) DL = MI->getDebugLoc();

47 if (RC == &MSP430::GR16RegClass)

51 else if (RC == &MSP430::GR8RegClass)

55 else

56 llvm_unreachable("Cannot store this register to stack slot!");

57}

61 Register DestReg, int FrameIdx,

66 if (MI != MBB.end()) DL = MI->getDebugLoc();

75 if (RC == &MSP430::GR16RegClass)

79 else if (RC == &MSP430::GR8RegClass)

83 else

84 llvm_unreachable("Cannot store this register to stack slot!");

85}

90 Register SrcReg, bool KillSrc,

91 bool RenamableDest, bool RenamableSrc) const {

92 unsigned Opc;

93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))

94 Opc = MSP430::MOV16rr;

95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))

96 Opc = MSP430::MOV8rr;

97 else

102}

103

105 int *BytesRemoved) const {

106 assert(!BytesRemoved && "code size not handled");

107

109 unsigned Count = 0;

110

111 while (I != MBB.begin()) {

112 --I;

113 if (I->isDebugInstr())

114 continue;

115 if (I->getOpcode() != MSP430::JMP &&

116 I->getOpcode() != MSP430::JCC &&

117 I->getOpcode() != MSP430::Bi &&

118 I->getOpcode() != MSP430::Br &&

119 I->getOpcode() != MSP430::Bm)

120 break;

121

122 I->eraseFromParent();

123 I = MBB.end();

125 }

126

128}

129

132 assert(Cond.size() == 1 && "Invalid Xbranch condition!");

133

135

136 switch (CC) {

140 break;

143 break;

146 break;

149 break;

152 break;

155 break;

156 }

157

158 Cond[0].setImm(CC);

159 return false;

160}

161

166 bool AllowModify) const {

167

168

170 while (I != MBB.begin()) {

171 --I;

172 if (I->isDebugInstr())

173 continue;

174

175

176

177 if (!isUnpredicatedTerminator(*I))

178 break;

179

180

181

182 if (->isBranch())

183 return true;

184

185

186 if (I->getOpcode() == MSP430::Br ||

187 I->getOpcode() == MSP430::Bm)

188 return true;

189

190

191 if (I->getOpcode() == MSP430::JMP || I->getOpcode() == MSP430::Bi) {

192 if (!AllowModify) {

193 TBB = I->getOperand(0).getMBB();

194 continue;

195 }

196

197

198 MBB.erase(std::next(I), MBB.end());

199 Cond.clear();

200 FBB = nullptr;

201

202

203 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {

204 TBB = nullptr;

205 I->eraseFromParent();

206 I = MBB.end();

207 continue;

208 }

209

210

211 TBB = I->getOperand(0).getMBB();

212 continue;

213 }

214

215

216 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");

220 return true;

221

222

223 if (Cond.empty()) {

224 FBB = TBB;

225 TBB = I->getOperand(0).getMBB();

227 continue;

228 }

229

230

231

234

235

236

237 if (TBB != I->getOperand(0).getMBB())

238 return true;

239

241

242 if (OldBranchCode == BranchCode)

243 continue;

244

245 return true;

246 }

247

248 return false;

249}

250

256 int *BytesAdded) const {

257

258 assert(TBB && "insertBranch must not be told to insert a fallthrough");

260 "MSP430 branch conditions have one component!");

261 assert(!BytesAdded && "code size not handled");

262

263 if (Cond.empty()) {

264

265 assert(!FBB && "Unconditional branch with multiple successors!");

267 return 1;

268 }

269

270

271 unsigned Count = 0;

274

275 if (FBB) {

276

279 }

281}

282

283

284

285

288

289 switch (Desc.getOpcode()) {

290 case TargetOpcode::CFI_INSTRUCTION:

291 case TargetOpcode::EH_LABEL:

292 case TargetOpcode::IMPLICIT_DEF:

293 case TargetOpcode::KILL:

294 case TargetOpcode::DBG_VALUE:

295 return 0;

296 case TargetOpcode::INLINEASM:

297 case TargetOpcode::INLINEASM_BR: {

300 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),

302 }

303 }

304

305 return Desc.getSize();

306}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Describe properties that are true of each instruction in the target description file.

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition MSP430InstrInfo.cpp:87

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition MSP430InstrInfo.cpp:251

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Definition MSP430InstrInfo.cpp:131

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition MSP430InstrInfo.cpp:59

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

GetInstSize - Return the number of bytes of code the specified instruction may be.

Definition MSP430InstrInfo.cpp:286

MSP430InstrInfo(const MSP430Subtarget &STI)

Definition MSP430InstrInfo.cpp:28

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Definition MSP430InstrInfo.cpp:162

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition MSP430InstrInfo.cpp:33

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition MSP430InstrInfo.cpp:104

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Representation of each machine instruction.

A description of a memory reference used in the backend.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

static MachineOperand CreateImm(int64_t Val)

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

TargetInstrInfo - Interface to description of machine instruction set.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

virtual const TargetInstrInfo * getInstrInfo() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

FunctionAddr VTableAddr Count

unsigned getDefRegState(bool B)

unsigned getKillRegState(bool B)

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.