LLVM: lib/Target/ARM/MVETailPredUtils.h Source File (original) (raw)
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15#ifndef LLVM_LIB_TARGET_ARM_MVETAILPREDUTILS_H
16#define LLVM_LIB_TARGET_ARM_MVETAILPREDUTILS_H
17
22
23namespace llvm {
24
25static inline unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop) {
26 switch (Opcode) {
27 default:
29 break;
30 case ARM::MVE_VCTP8:
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;
32 case ARM::MVE_VCTP16:
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16;
34 case ARM::MVE_VCTP32:
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32;
36 case ARM::MVE_VCTP64:
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64;
38 }
39 return 0;
40}
41
43 switch (Opcode) {
44 default:
46 case ARM::MVE_VCTP8:
47 return 16;
48 case ARM::MVE_VCTP16:
49 return 8;
50 case ARM::MVE_VCTP32:
51 return 4;
52 case ARM::MVE_VCTP64:
53 return 2;
54 }
55 return 0;
56}
57
59 switch (MI->getOpcode()) {
60 default:
61 break;
62 case ARM::MVE_VCTP8:
63 case ARM::MVE_VCTP16:
64 case ARM::MVE_VCTP32:
65 case ARM::MVE_VCTP64:
66 return true;
67 }
68 return false;
69}
70
72 return MI.getOpcode() == ARM::t2DoLoopStart ||
73 MI.getOpcode() == ARM::t2DoLoopStartTP;
74}
75
77 return MI.getOpcode() == ARM::t2WhileLoopStart ||
78 MI.getOpcode() == ARM::t2WhileLoopStartLR ||
79 MI.getOpcode() == ARM::t2WhileLoopStartTP;
80}
81
85
86
89 unsigned Op = MI.getOpcode() == ARM::t2WhileLoopStartTP ? 3 : 2;
90 return MI.getOperand(Op).getMBB();
91}
92
93
94
95
96
97
99 unsigned BrOpc = ARM::t2Bcc,
100 bool UseCmp = false) {
102 assert((MI->getOpcode() == ARM::t2WhileLoopStartLR ||
103 MI->getOpcode() == ARM::t2WhileLoopStartTP) &&
104 "Only expected a t2WhileLoopStartLR/TP in RevertWhileLoopStartLR!");
105
106
107 if (UseCmp) {
110 MIB.add(MI->getOperand(1));
113 MIB.addReg(ARM::NoRegister);
114 } else {
117 MIB.add(MI->getOperand(0));
118 MIB.add(MI->getOperand(1));
121 MIB.addReg(ARM::NoRegister);
123 }
124
125
130 MIB.addReg(ARM::CPSR);
131
132 MI->eraseFromParent();
133}
134
141
142 MI->eraseFromParent();
143}
144
146 bool SetFlags = false) {
148
151 MIB.add(MI->getOperand(0));
152 MIB.add(MI->getOperand(1));
153 MIB.add(MI->getOperand(2));
156
157 if (SetFlags) {
158 MIB.addReg(ARM::CPSR);
160 } else
162
163 MI->eraseFromParent();
164}
165
166
168 unsigned BrOpc = ARM::t2Bcc, bool SkipCmp = false) {
170
171
172 if (!SkipCmp) {
175 MIB.add(MI->getOperand(0));
178 MIB.addReg(ARM::NoRegister);
179 }
180
181
184 MIB.add(MI->getOperand(1));
186 MIB.addReg(ARM::CPSR);
187 MI->eraseFromParent();
188}
189
190}
191
192#endif
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
LLVM_ABI void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
TargetInstrInfo - Interface to description of machine instruction set.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Define
Register definition.
This is an optimization pass for GlobalISel generic memory operations.
static bool isDoLoopStart(const MachineInstr &MI)
Definition MVETailPredUtils.h:71
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isVCTP(const MachineInstr *MI)
Definition MVETailPredUtils.h:58
static unsigned getTailPredVectorWidth(unsigned Opcode)
Definition MVETailPredUtils.h:42
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isLoopStart(const MachineInstr &MI)
Definition MVETailPredUtils.h:82
void RevertWhileLoopStartLR(MachineInstr *MI, const TargetInstrInfo *TII, unsigned BrOpc=ARM::t2Bcc, bool UseCmp=false)
Definition MVETailPredUtils.h:98
static unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop)
Definition MVETailPredUtils.h:25
DWARFExpression::Operation Op
void RevertLoopEnd(MachineInstr *MI, const TargetInstrInfo *TII, unsigned BrOpc=ARM::t2Bcc, bool SkipCmp=false)
Definition MVETailPredUtils.h:167
void RevertLoopDec(MachineInstr *MI, const TargetInstrInfo *TII, bool SetFlags=false)
Definition MVETailPredUtils.h:145
MachineBasicBlock * getWhileLoopStartTargetBB(const MachineInstr &MI)
Definition MVETailPredUtils.h:87
static bool isWhileLoopStart(const MachineInstr &MI)
Definition MVETailPredUtils.h:76
void RevertDoLoopStart(MachineInstr *MI, const TargetInstrInfo *TII)
Definition MVETailPredUtils.h:135