MachineCSE.cpp Source File (original) (raw)

45#include

46#include

47#include

49using namespace llvm;

51#define DEBUG_TYPE "machine-cse"

53 STATISTIC(NumCoalesces, "Number of copies coalesced");

54 STATISTIC(NumCSEs, "Number of common subexpression eliminated");

55 STATISTIC(NumPREs, "Number of partial redundant expression"

56 " transformed to fully redundant");

58 "Number of physreg referencing common subexpr eliminated");

60 "Number of cross-MBB physreg referencing CS eliminated");

61 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");

66 cl::desc("Threshold for the size of CSUses"));

70 cl::desc("Override the profitability heuristics for Machine CSE"));

72namespace {

74class MachineCSEImpl {

81public:

83 : DT(DT), MBFI(MBFI) {}

84 bool run(MachineFunction &MF);

86private:

87 using AllocatorTy =

89 ScopedHashTableVal<MachineInstr *, unsigned>>;

90 using ScopedHTType =

91 ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,

92 AllocatorTy>;

96 unsigned LookAheadLimit = 0;

97 DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;

98 DenseMap<MachineInstr *, MachineBasicBlock *, MachineInstrExpressionTrait>

99 PREMap;

100 ScopedHTType VNT;

102 unsigned CurrVN = 0;

103

104 bool PerformTrivialCopyPropagation(MachineInstr *MI, MachineBasicBlock *MBB);

105 bool isPhysDefTriviallyDead(MCRegister Reg,

108 bool hasLivePhysRegDefUses(const MachineInstr *MI,

109 const MachineBasicBlock *MBB,

110 SmallSet<MCRegister, 8> &PhysRefs,

111 PhysDefVector &PhysDefs, bool &PhysUseDef) const;

112 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,

113 const SmallSet<MCRegister, 8> &PhysRefs,

114 const PhysDefVector &PhysDefs, bool &NonLocal) const;

115 bool isCSECandidate(MachineInstr *MI);

116 bool isProfitableToCSE(Register CSReg, Register Reg, MachineBasicBlock *CSBB,

117 MachineInstr *MI);

118 void EnterScope(MachineBasicBlock *MBB);

119 void ExitScope(MachineBasicBlock *MBB);

120 bool ProcessBlockCSE(MachineBasicBlock *MBB);

122 DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren);

124

125 bool isPRECandidate(MachineInstr *MI, SmallSet<MCRegister, 8> &PhysRefs);

126 bool ProcessBlockPRE(MachineDominatorTree *MDT, MachineBasicBlock *MBB);

127 bool PerformSimplePRE(MachineDominatorTree *DT);

128

129

130 bool isProfitableToHoistInto(MachineBasicBlock *CandidateBB,

131 MachineBasicBlock *MBB, MachineBasicBlock *MBB1);

132 void releaseMemory();

133};

134

136public:

137 static char ID;

138

139 MachineCSELegacy() : MachineFunctionPass(ID) {

141 }

142

143 bool runOnMachineFunction(MachineFunction &MF) override;

144

145 void getAnalysisUsage(AnalysisUsage &AU) const override {

149 AU.addRequired();

150 AU.addPreserved();

151 AU.addRequired();

152 AU.addPreserved();

153 }

154

155 MachineFunctionProperties getRequiredProperties() const override {

156 return MachineFunctionProperties().setIsSSA();

157 }

158};

159}

160

161char MachineCSELegacy::ID = 0;

162

164

166 "Machine Common Subexpression Elimination", false, false)

169 "Machine Common Subexpression Elimination", false, false)

170

171

172

173

174

175bool MachineCSEImpl::PerformTrivialCopyPropagation(MachineInstr *MI,

179 Register Reg = MO.getReg();

180 if (!Reg.isVirtual())

181 continue;

182 bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);

183 MachineInstr *DefMI = MRI->getVRegDef(Reg);

184 if (!DefMI || !DefMI->isCopy())

185 continue;

186 Register SrcReg = DefMI->getOperand(1).getReg();

187 if (!SrcReg.isVirtual())

188 continue;

189

190

191

192

193

194

195

196

197

198

199

200

201 if (DefMI->getOperand(1).getSubReg())

202 continue;

203 if (!MRI->constrainRegAttrs(SrcReg, Reg))

204 continue;

205 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);

206 LLVM_DEBUG(dbgs() << "*** to: " << *MI);

207

208

209 MO.setReg(SrcReg);

210 MRI->clearKillFlags(SrcReg);

211

212 if (OnlyOneUse) {

213

214

215

216 DefMI->changeDebugValuesDefReg(SrcReg);

217

218 DefMI->eraseFromParent();

219 ++NumCoalesces;

220 }

222 }

223

225}

226

227bool MachineCSEImpl::isPhysDefTriviallyDead(

230 unsigned LookAheadLeft = LookAheadLimit;

231 while (LookAheadLeft) {

232

234

235 if (I == E)

236

237 return false;

238

239 bool SeenDef = false;

240 for (const MachineOperand &MO : I->operands()) {

241 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))

242 SeenDef = true;

243 if (!MO.isReg() || !MO.getReg())

244 continue;

245 if ( TRI ->regsOverlap(MO.getReg(), Reg))

246 continue;

247 if (MO.isUse())

248

249 return false;

250 SeenDef = true;

251 }

252 if (SeenDef)

253

254

255 return true;

256

257 --LookAheadLeft;

258 ++I;

259 }

260 return false;

261}

262

268

269

270

271

272

273

274

276 return TRI.isCallerPreservedPhysReg(Reg, MF) || TII.isIgnorableUse(MO) ||

277 (MRI.reservedRegsFrozen() && MRI.isConstantPhysReg(Reg));

278}

279

280

281

282

283

284bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,

285 const MachineBasicBlock *MBB,

286 SmallSet<MCRegister, 8> &PhysRefs,

287 PhysDefVector &PhysDefs,

288 bool &PhysUseDef) const {

289

290 for (const MachineOperand &MO : MI->all_uses()) {

292 if ( Reg )

293 continue;

295 continue;

296

299 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)

300 PhysRefs.insert(*AI);

301 }

302

303

304

305 PhysUseDef = false;

308 const MachineOperand &MO = MOP.value();

310 continue;

312 if ( Reg )

313 continue;

315 continue;

316

318 PhysUseDef = true;

319

320

321

323 PhysDefs.emplace_back(MOP.index(), Reg);

324 }

325

326

327 for (const auto &Def : PhysDefs)

328 for (MCRegAliasIterator AI(Def.second, TRI, true); AI.isValid(); ++AI)

329 PhysRefs.insert(*AI);

330

331 return !PhysRefs.empty();

332}

333

334bool MachineCSEImpl::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,

335 const SmallSet<MCRegister, 8> &PhysRefs,

336 const PhysDefVector &PhysDefs,

337 bool &NonLocal) const {

338

339

340

341 const MachineBasicBlock *MBB = MI->getParent();

342 const MachineBasicBlock *CSMBB = CSMI->getParent();

343

344 bool CrossMBB = false;

345 if (CSMBB != MBB) {

347 return false;

348

349 for (const auto &PhysDef : PhysDefs) {

350 if (MRI->isAllocatable(PhysDef.second) || MRI->isReserved(PhysDef.second))

351

352

353 return false;

354 }

355 CrossMBB = true;

356 }

360 unsigned LookAheadLeft = LookAheadLimit;

361 while (LookAheadLeft) {

362

363 while (I != E && I != EE && I->isDebugInstr())

364 ++I;

365

366 if (I == EE) {

367 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");

368 (void)CrossMBB;

369 CrossMBB = false;

370 NonLocal = true;

373 continue;

374 }

375

376 if (I == E)

377 return true;

378

379 for (const MachineOperand &MO : I->operands()) {

380

381

383 return false;

385 continue;

388 continue;

390 return false;

391 }

392

393 --LookAheadLeft;

394 ++I;

395 }

396

397 return false;

398}

399

400bool MachineCSEImpl::isCSECandidate(MachineInstr *MI) {

401 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||

402 MI->isInlineAsm() || MI->isDebugInstr() || MI->isJumpTableDebugInfo() ||

403 MI->isFakeUse())

404 return false;

405

406

407 if (MI->isCopyLike())

408 return false;

409

410

411 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||

412 MI->mayRaiseFPException() || MI->hasUnmodeledSideEffects())

413 return false;

414

415 if (MI->mayLoad()) {

416

417

418

419 if (->isDereferenceableInvariantLoad())

420

421

422

423 return false;

424 }

425

426

427

428 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD)

429 return false;

430

431 return true;

432}

433

434

435

436

438 MachineBasicBlock *CSBB,

439 MachineInstr *MI) {

441 return true;

442

443

444

445

446

447 bool MayIncreasePressure = true;

449 MayIncreasePressure = false;

450 SmallPtrSet<MachineInstr*, 8> CSUses;

451 int NumOfUses = 0;

452 for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {

454

455

457 MayIncreasePressure = true;

458 break;

459 }

460 }

461 if (!MayIncreasePressure)

462 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {

463 if (!CSUses.count(&MI)) {

464 MayIncreasePressure = true;

465 break;

466 }

467 }

468 }

469 if (!MayIncreasePressure) return true;

470

471

472

473

475 MachineBasicBlock *BB = MI->getParent();

476 if (CSBB != BB && !CSBB->isSuccessor(BB))

477 return false;

478 }

479

480

481

482 bool HasVRegUse = false;

483 for (const MachineOperand &MO : MI->all_uses()) {

485 HasVRegUse = true;

486 break;

487 }

488 }

489 if (!HasVRegUse) {

490 bool HasNonCopyUse = false;

491 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {

492

493 if (.isCopyLike()) {

494 HasNonCopyUse = true;

495 break;

496 }

497 }

498 if (!HasNonCopyUse)

499 return false;

500 }

501

502

503

504 bool HasPHI = false;

505 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {

506 HasPHI |= UseMI.isPHI();

507 if (UseMI.getParent() == MI->getParent())

508 return true;

509 }

510

511 return !HasPHI;

512}

513

514void MachineCSEImpl::EnterScope(MachineBasicBlock *MBB) {

516 ScopeType *Scope = new ScopeType(VNT);

518}

519

520void MachineCSEImpl::ExitScope(MachineBasicBlock *MBB) {

522 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);

523 assert(SI != ScopeMap.end());

524 delete SI->second;

525 ScopeMap.erase(SI);

526}

527

528bool MachineCSEImpl::ProcessBlockCSE(MachineBasicBlock *MBB) {

530

532 SmallVector<unsigned, 2> ImplicitDefsToUpdate;

535 if (!isCSECandidate(&MI))

536 continue;

537

538 bool FoundCSE = VNT.count(&MI);

539 if (!FoundCSE) {

540

541 if (PerformTrivialCopyPropagation(&MI, MBB)) {

543

544

545 if (MI.isCopyLike())

546 continue;

547

548

549 FoundCSE = VNT.count(&MI);

550 }

551 }

552

553

554 bool Commuted = false;

555 if (!FoundCSE && MI.isCommutable()) {

557 Commuted = true;

558 FoundCSE = VNT.count(NewMI);

559 if (NewMI != &MI) {

560

561 NewMI->eraseFromParent();

563 } else if (!FoundCSE)

564

566 }

567 }

568

569

570

571

572 bool CrossMBBPhysDef = false;

573 SmallSet<MCRegister, 8> PhysRefs;

574 PhysDefVector PhysDefs;

575 bool PhysUseDef = false;

576 if (FoundCSE &&

577 hasLivePhysRegDefUses(&MI, MBB, PhysRefs, PhysDefs, PhysUseDef)) {

578 FoundCSE = false;

579

580

581

582

583

584

585 if (!PhysUseDef) {

586 unsigned CSVN = VNT.lookup(&MI);

587 MachineInstr *CSMI = Exps[CSVN];

588 if (PhysRegDefsReach(CSMI, &MI, PhysRefs, PhysDefs, CrossMBBPhysDef))

589 FoundCSE = true;

590 }

591 }

592

593 if (!FoundCSE) {

595 Exps.push_back(&MI);

596 continue;

597 }

598

599

600 unsigned CSVN = VNT.lookup(&MI);

601 MachineInstr *CSMI = Exps[CSVN];

603 LLVM_DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);

604

605

606

607

608

609

610

611

612

613

614 if (MI.isConvergent() && MI.getParent() != CSMI->getParent()) {

615 LLVM_DEBUG(dbgs() << "*** Convergent MI and subexpression exist in "

616 "different BBs, avoid CSE!\n");

618 Exps.push_back(&MI);

619 continue;

620 }

621

622

623 bool DoCSE = true;

624 unsigned NumDefs = MI.getNumDefs();

625

626 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {

627 MachineOperand &MO = MI.getOperand(i);

629 continue;

632

633

634

636 ImplicitDefsToUpdate.push_back(i);

637

638

639

642

643 if (OldReg == NewReg) {

644 --NumDefs;

645 continue;

646 }

647

649 "Do not CSE physical register defs!");

650

651 if (!isProfitableToCSE(NewReg, OldReg, CSMI->getParent(), &MI)) {

652 LLVM_DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");

653 DoCSE = false;

654 break;

655 }

656

657

658

659

660 if ( MRI ->constrainRegAttrs(NewReg, OldReg)) {

662 dbgs() << "*** Not the same register constraints, avoid CSE!\n");

663 DoCSE = false;

664 break;

665 }

666

668 --NumDefs;

669 }

670

671

672 if (DoCSE) {

673 for (const std::pair<Register, Register> &CSEPair : CSEPairs) {

674 Register OldReg = CSEPair.first;

675 Register NewReg = CSEPair.second;

676

677 MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);

678 assert(Def != nullptr && "CSEd register has no unique definition?");

679 Def->clearRegisterDeads(NewReg);

680

681 MRI->replaceRegWith(OldReg, NewReg);

682 MRI->clearKillFlags(NewReg);

683 }

684

685

686

687 for (unsigned ImplicitDefToUpdate : ImplicitDefsToUpdate)

689 for (const auto &PhysDef : PhysDefs)

690 if (.getOperand(PhysDef.first).isDead())

692

693

694

695

696

697

698

699

700

701

702

703 if (CSMI->getParent() == MI.getParent()) {

705 for (auto ImplicitDef : ImplicitDefs)

706 if (MachineOperand *MO = II->findRegisterUseOperand(

707 ImplicitDef, TRI, true))

709 } else {

710

711

712 for (auto ImplicitDef : ImplicitDefs)

713 MRI->clearKillFlags(ImplicitDef);

714 }

715

716 if (CrossMBBPhysDef) {

717

718

719 while (!PhysDefs.empty()) {

720 auto LiveIn = PhysDefs.pop_back_val();

723 }

724 ++NumCrossBBCSEs;

725 }

726

727 MI.eraseFromParent();

728 ++NumCSEs;

729 if (!PhysRefs.empty())

730 ++NumPhysCSEs;

731 if (Commuted)

732 ++NumCommutes;

734 } else {

736 Exps.push_back(&MI);

737 }

738 CSEPairs.clear();

739 ImplicitDefsToUpdate.clear();

740 ImplicitDefs.clear();

741 }

742

744}

745

746

747

748

749void MachineCSEImpl::ExitScopeIfDone(

751 DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren) {

752 if (OpenChildren[Node])

753 return;

754

755

756 ExitScope(Node->getBlock());

757

758

760 unsigned Left = --OpenChildren[Parent];

761 if (Left != 0)

762 break;

763 ExitScope(Parent->getBlock());

764 Node = Parent;

765 }

766}

767

771 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;

772

773 CurrVN = 0;

774

775

777 do {

779 Scopes.push_back(Node);

780 OpenChildren[Node] = Node->getNumChildren();

782 } while (!WorkList.empty());

783

784

787 MachineBasicBlock *MBB = Node->getBlock();

788 EnterScope(MBB);

790

791 ExitScopeIfDone(Node, OpenChildren);

792 }

793

795}

796

797

798

799

800bool MachineCSEImpl::isPRECandidate(MachineInstr *MI,

801 SmallSet<MCRegister, 8> &PhysRefs) {

802 if (!isCSECandidate(MI) ||

803 MI->isNotDuplicable() ||

804 MI->mayLoad() ||

806 MI->getNumDefs() != 1 ||

807 MI->getNumExplicitDefs() != 1)

808 return false;

809

810 for (const MachineOperand &MO : MI->operands()) {

813 return false;

814 else

816 }

817 }

818

819 return true;

820}

821

822bool MachineCSEImpl::ProcessBlockPRE(MachineDominatorTree *DT,

823 MachineBasicBlock *MBB) {

826 SmallSet<MCRegister, 8> PhysRefs;

827 if (!isPRECandidate(&MI, PhysRefs))

828 continue;

829

830 auto [It, Inserted] = PREMap.try_emplace(&MI, MBB);

831 if (Inserted)

832 continue;

833

834 auto *MBB1 = It->second;

837 "MBB cannot properly dominate MBB1 while DFS through dominators tree!");

839 if (!CMBB->isLegalToHoistInto())

840 continue;

841

842 if (!isProfitableToHoistInto(CMBB, MBB, MBB1))

843 continue;

844

845

846

847 if (CMBB != MBB1) {

849 if (BB != nullptr && BB1 != nullptr &&

852

853

854

855

856

857

858

859 if (MI.isConvergent() && CMBB != MBB)

860 continue;

861

862

863

864 bool NonLocal;

865 PhysDefVector PhysDefs;

866 if (!PhysRefs.empty() &&

867 !PhysRegDefsReach(&*(CMBB->getFirstTerminator()), &MI, PhysRefs,

868 PhysDefs, NonLocal))

869 continue;

870

871 assert(MI.getOperand(0).isDef() &&

872 "First operand of instr with one explicit def must be this def");

873 Register VReg = MI.getOperand(0).getReg();

874 Register NewReg = MRI->cloneVirtualRegister(VReg);

875 if (!isProfitableToCSE(NewReg, VReg, CMBB, &MI))

876 continue;

877 MachineInstr &NewMI =

878 TII->duplicate(*CMBB, CMBB->getFirstTerminator(), MI);

879

880

881

882

885

887

888 PREMap[&MI] = CMBB;

889 ++NumPREs;

891 }

892 }

893 }

895}

896

897

898

899

900

901

902bool MachineCSEImpl::PerformSimplePRE(MachineDominatorTree *DT) {

904

905 PREMap.clear();

908 do {

911

912 MachineBasicBlock *MBB = Node->getBlock();

914

915 } while (!BBs.empty());

916

918}

919

920bool MachineCSEImpl::isProfitableToHoistInto(MachineBasicBlock *CandidateBB,

921 MachineBasicBlock *MBB,

922 MachineBasicBlock *MBB1) {

924 return true;

925 assert(DT->dominates(CandidateBB, MBB) && "CandidateBB should dominate MBB");

927 "CandidateBB should dominate MBB1");

930}

931

932void MachineCSEImpl::releaseMemory() {

933 ScopeMap.clear();

934 PREMap.clear();

935 Exps.clear();

936}

937

938bool MachineCSEImpl::run(MachineFunction &MF) {

943 bool ChangedPRE, ChangedCSE;

944 ChangedPRE = PerformSimplePRE(DT);

945 ChangedCSE = PerformCSE(DT->getRootNode());

946 releaseMemory();

947 return ChangedPRE || ChangedCSE;

948}

949

953

957 MachineCSEImpl Impl(&MDT, &MBFI);

958 bool Changed = Impl.run(MF);

961

967 return PA;

968}

969

970bool MachineCSELegacy::runOnMachineFunction(MachineFunction &MF) {

972 return false;

973

975 getAnalysis().getDomTree();

977 getAnalysis().getMBFI();

978 MachineCSEImpl Impl(&MDT, &MBFI);

979 return Impl.run(MF);

980}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file defines the BumpPtrAllocator interface.

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

This file defines the DenseMap class.

static bool isCallerPreservedOrConstPhysReg(MCRegister Reg, const MachineOperand &MO, const MachineFunction &MF, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)

Definition MachineCSE.cpp:263

static cl::opt< int > CSUsesThreshold("csuses-threshold", cl::Hidden, cl::init(1024), cl::desc("Threshold for the size of CSUses"))

static cl::opt< bool > AggressiveMachineCSE("aggressive-machine-cse", cl::Hidden, cl::init(false), cl::desc("Override the profitability heuristics for Machine CSE"))

Promote Memory to Register

uint64_t IntrinsicInst * II

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file defines the SmallPtrSet class.

This file defines the SmallSet class.

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

AnalysisUsage & addPreservedID(const void *ID)

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

Represents analyses that only rely on functions' control flow.

DomTreeNodeBase< NodeT > * getRootNode()

getRootNode - This returns the entry node for the CFG of the function.

NodeT * findNearestCommonDominator(NodeT *A, NodeT *B) const

Find nearest common dominator basic block for basic block A and B.

bool properlyDominates(const DomTreeNodeBase< NodeT > *A, const DomTreeNodeBase< NodeT > *B) const

properlyDominates - Returns true iff A dominates B and A != B.

bool hasMinSize() const

Optimize this function for minimum size (-Oz).

Wrapper class representing physical registers. Should be passed by value.

An RAII based helper class to modify MachineFunctionProperties when running pass.

unsigned pred_size() const

MachineInstrBundleIterator< const MachineInstr > const_iterator

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

pred_iterator pred_begin()

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB is a successor of this block.

MachineInstrBundleIterator< MachineInstr > iterator

LLVM_ABI StringRef getName() const

Return the name of the corresponding LLVM basic block, or an empty string.

LLVM_ABI bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const

Return true if the specified register is in the live in set.

MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...

LLVM_ABI BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const

getblockFreq - Return block frequency.

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition MachineCSE.cpp:950

Analysis pass which computes a MachineDominatorTree.

DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...

bool dominates(const MachineInstr *A, const MachineInstr *B) const

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

const MachineBasicBlock * getParent() const

const MachineOperand & getOperand(unsigned i) const

void setDebugLoc(DebugLoc DL)

Replace current source information with new such.

Analysis pass that exposes the MachineLoopInfo for a machine function.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

void setIsDead(bool Val=true)

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

void setIsKill(bool Val=true)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

MCRegister asMCReg() const

Utility to check-convert this value to a MCRegister.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

size_type count(const K &Key) const

Return 1 if the specified key is in the table, 0 otherwise.

void insert(const K &Key, const V &Val)

V lookup(const K &Key) const

ScopedHashTableScope< MachineInstr *, unsigned, MachineInstrExpressionTrait, AllocatorTy > ScopeTy

size_type count(ConstPtrType Ptr) const

count - Return 1 if the specified pointer is in the set, 0 otherwise.

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

size_type count(const T &V) const

count - Return 1 if the element is in the set, 0 otherwise.

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

reference emplace_back(ArgTypes &&... Args)

void push_back(const T &Elt)

TargetInstrInfo - Interface to description of machine instruction set.

virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const

Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.

virtual bool isAsCheapAsAMove(const MachineInstr &MI) const

Return true if the instruction is as cheap as a move instruction.

MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const

This method commutes the operands of the given machine instruction MI.

virtual unsigned getMachineCSELookAheadLimit() const

Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

initializer< Ty > init(const Ty &Val)

PointerTypeMap run(const Module &M)

Compute the PointerTypeMap for the module M.

Scope

Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...

NodeAddr< DefNode * > Def

NodeAddr< NodeBase * > Node

This is an optimization pass for GlobalISel generic memory operations.

auto enumerate(FirstRange &&First, RestRanges &&...Rest)

Given two or more input ranges, returns a new range whose values are tuples (A, B,...

void append_range(Container &C, Range &&R)

Wrapper function to append range R to container C.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()

Returns the minimum set of Analyses that all machine function passes must preserve.

IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)

Increment It until it points to a non-debug instruction or to End and return the resulting iterator.

LLVM_ABI char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

LLVM_ABI void initializeMachineCSELegacyPass(PassRegistry &)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

DomTreeNodeBase< MachineBasicBlock > MachineDomTreeNode

LLVM_ABI char & MachineCSELegacyID

MachineCSE - This pass performs global CSE on machine instructions.

Definition MachineCSE.cpp:163

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

LLVM_ABI bool isPotentiallyReachable(const Instruction *From, const Instruction *To, const SmallPtrSetImpl< BasicBlock * > *ExclusionSet=nullptr, const DominatorTree *DT=nullptr, const LoopInfo *LI=nullptr)

Determine whether instruction 'To' is reachable from 'From', without passing through any blocks in Ex...