LLVM: include/llvm/CodeGen/MachineInstr.h Source File (original) (raw)
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15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
34#include
35#include
36#include
37#include
38
39namespace llvm {
40
41class DILabel;
42class Instruction;
43class MDNode;
44class AAResults;
45template class ArrayRef;
46class DIExpression;
47class DILocalVariable;
48class MachineBasicBlock;
49class MachineFunction;
50class MachineRegisterInfo;
51class ModuleSlotTracker;
52class raw_ostream;
53template class SmallVectorImpl;
54class SmallBitVector;
55class StringRef;
56class TargetInstrInfo;
57class TargetRegisterClass;
58class TargetRegisterInfo;
59
60
61
62
63
64
65
66
69 ilist_sentinel_tracking> {
70public:
72
73
74
75
76
78 ReloadReuse = 0x1,
80 TAsmComments = 0x4
82
85 FrameSetup = 1 << 0,
86
87 FrameDestroy = 1 << 1,
88
89 BundledPred = 1 << 2,
90 BundledSucc = 1 << 3,
92
94
96
98
99 FmContract = 1 << 8,
100
102
104
106
108
110
111 NoFPExcept = 1 << 14,
112
114
115
116 Unpredictable = 1 << 16,
117 NoConvergent = 1 << 17,
121
122 SameSign = 1 << 21
124
125private:
126 const MCInstrDesc *MCID;
127 MachineBasicBlock *Parent = nullptr;
128
129
130 MachineOperand *Operands = nullptr;
131
132#define LLVM_MI_NUMOPERANDS_BITS 24
133#define LLVM_MI_FLAGS_BITS 24
134#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
135
136
138
139
140
141 using OperandCapacity = ArrayRecycler::Capacity;
142 OperandCapacity CapOperands;
143
144
146
147
148
149
151
152
153
154
155
156
157
158 class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
159 MCSymbol *, MDNode *, uint32_t> {
160 public:
162 ArrayRef<MachineMemOperand *> MMOs,
163 MCSymbol *PreInstrSymbol = nullptr,
164 MCSymbol *PostInstrSymbol = nullptr,
165 MDNode *HeapAllocMarker = nullptr,
166 MDNode *PCSections = nullptr, uint32_t CFIType = 0,
167 MDNode *MMRAs = nullptr) {
168 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
169 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
170 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
171 bool HasMMRAs = MMRAs != nullptr;
172 bool HasCFIType = CFIType != 0;
173 bool HasPCSections = PCSections != nullptr;
174 auto *Result = new (Allocator.Allocate(
175 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
176 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
177 HasHeapAllocMarker + HasPCSections + HasMMRAs, HasCFIType),
178 alignof(ExtraInfo)))
179 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
180 HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs);
181
182
183 std::copy(MMOs.begin(), MMOs.end(),
184 Result->getTrailingObjects<MachineMemOperand *>());
185
186 unsigned MDNodeIdx = 0;
187
188 if (HasPreInstrSymbol)
189 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
190 if (HasPostInstrSymbol)
191 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
192 PostInstrSymbol;
193 if (HasHeapAllocMarker)
194 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = HeapAllocMarker;
195 if (HasPCSections)
196 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = PCSections;
197 if (HasCFIType)
198 Result->getTrailingObjects<uint32_t>()[0] = CFIType;
199 if (HasMMRAs)
200 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = MMRAs;
201
202 return Result;
203 }
204
205 ArrayRef<MachineMemOperand *> getMMOs() const {
206 return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
207 }
208
209 MCSymbol *getPreInstrSymbol() const {
210 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
211 }
212
213 MCSymbol *getPostInstrSymbol() const {
214 return HasPostInstrSymbol
215 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
216 : nullptr;
217 }
218
219 MDNode *getHeapAllocMarker() const {
220 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
221 }
222
223 MDNode *getPCSections() const {
224 return HasPCSections
225 ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
226 : nullptr;
227 }
228
229 uint32_t getCFIType() const {
230 return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
231 }
232
233 MDNode *getMMRAMetadata() const {
234 return HasMMRAs ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker +
235 HasPCSections]
236 : nullptr;
237 }
238
239 private:
240 friend TrailingObjects;
241
242
243
244
245
246
247 const int NumMMOs;
248 const bool HasPreInstrSymbol;
249 const bool HasPostInstrSymbol;
250 const bool HasHeapAllocMarker;
251 const bool HasPCSections;
252 const bool HasCFIType;
253 const bool HasMMRAs;
254
255
256 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
257 return NumMMOs;
258 }
259 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
260 return HasPreInstrSymbol + HasPostInstrSymbol;
261 }
262 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
263 return HasHeapAllocMarker + HasPCSections;
264 }
265 size_t numTrailingObjects(OverloadToken<uint32_t>) const {
266 return HasCFIType;
267 }
268
269
270
271 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
272 bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType,
273 bool HasMMRAs)
274 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
275 HasPostInstrSymbol(HasPostInstrSymbol),
276 HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
277 HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {}
278 };
279
280
281
282
283 enum ExtraInfoInlineKinds {
284 EIIK_MMO = 0,
285 EIIK_PreInstrSymbol,
286 EIIK_PostInstrSymbol,
287 EIIK_OutOfLine
288 };
289
290
291
292
293
294
295 PointerSumType<ExtraInfoInlineKinds,
296 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
297 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
298 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
299 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
300 Info;
301
302 DebugLoc DbgLoc;
303
304
305
306 unsigned DebugInstrNum;
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324 bool NoImp = false);
325
326
328
329 void
332
334 return Op.isReg() && Op.isDef();
335 }
336
338 return Op.isReg() && Op.isUse();
339 }
340
341public:
344
346
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350
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356
357
362 }
363
364
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369
370
372 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
373 "Flag is out of range for the AsmPrinterFlags field");
374 return AsmPrinterFlags & Flag;
375 }
376
377
379 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
380 "Flag is out of range for the AsmPrinterFlags field");
381 AsmPrinterFlags |= Flag;
382 }
383
384
386 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
387 "Flag is out of range for the AsmPrinterFlags field");
388 AsmPrinterFlags &= ~Flag;
389 }
390
391
393 return Flags;
394 }
395
396
398 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
399 "Flag is out of range for the Flags field");
400 return Flags & Flag;
401 }
402
403
405 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
406 "Flag is out of range for the Flags field");
408 }
409
411 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
412 "flags to be set are out of range for the Flags field");
413
415 Flags = (Flags & Mask) | (flags & ~Mask);
416 }
417
418
420 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
421 "Flag to clear is out of range for the Flags field");
423 }
424
426 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
427 "flags to be cleared are out of range for the Flags field");
428 Flags &= ~flags;
429 }
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468 }
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474 }
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507 }
511 }
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575 unsigned getOpcode() const { return Opcode; }
576
577
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580
583 }
584
588 }
592 }
593
597 }
601 }
602
603
604
607 return Op.isReg() && Op.getReg() == Reg;
608 });
609 }
610
611
612
613 template <typename Operand, typename Instruction>
617 std::function<bool(Operand & Op)> OpUsesReg(
618 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
620 }
626 }
630 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
631 this, Reg);
632 }
633
636 }
637
641 }
642
643
646 }
647
648
651 if (MO.isDef())
652 return true;
653 return false;
654 }
655
656
659 }
660
661
665 return true;
667 return true;
668 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
669 return true;
671 return true;
672 return false;
673 }
674
675
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681
684
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690
693 }
696 }
700 }
704 }
707 }
710 }
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718 }
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725 }
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731 }
732
736 }
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741 }
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745 }
749 }
753 }
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764 }
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768 }
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774 }
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778 }
779
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783 }
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787
790 return {};
791
792 if (Info.is<EIIK_MMO>())
793 return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
794
795 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
796 return EI->getMMOs();
797
798 return {};
799 }
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829 return nullptr;
830 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
831 return S;
832 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
833 return EI->getPreInstrSymbol();
834
835 return nullptr;
836 }
837
838
841 return nullptr;
842 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
843 return S;
844 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
845 return EI->getPostInstrSymbol();
846
847 return nullptr;
848 }
849
850
853 return nullptr;
854 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
855 return EI->getHeapAllocMarker();
856
857 return nullptr;
858 }
859
860
863 return nullptr;
864 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
865 return EI->getPCSections();
866
867 return nullptr;
868 }
869
870
873 return nullptr;
874 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
875 return EI->getMMRAMetadata();
876 return nullptr;
877 }
878
879
882 return 0;
883 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
884 return EI->getCFIType();
885
886 return 0;
887 }
888
889
890
891
895 AllInBundle
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904 assert(MCFlag < 64 &&
905 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
906
909
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911 return hasPropertyInBundle(1ULL << MCFlag, Type);
912 }
913
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915
918 }
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1057 return true;
1059 }
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1068 return true;
1069 }
1071 return false;
1073 }
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1120 }
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1147 return true;
1148 }
1150 }
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1160 return true;
1161 }
1163 }
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1168 }
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1179 }
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1197 }
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1276 }
1277
1282 IgnoreVRegDefs
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1330 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1331 }
1332
1334 return getOpcode() == TargetOpcode::LIFETIME_START ||
1335 getOpcode() == TargetOpcode::LIFETIME_END;
1336 }
1337
1338
1341 }
1342
1344 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1345 }
1346
1348 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1349 }
1350
1351
1353
1355 return getOpcode() == TargetOpcode::DBG_VALUE;
1356 }
1358 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1359 }
1362 }
1369 }
1372 }
1373
1376 }
1377
1378
1379
1382 }
1383
1384
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1388
1389
1392 return false;
1393
1395 if (Op.isReg() && .getReg().isValid())
1396 return true;
1397 return false;
1398 }
1399
1401 return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1402 }
1403
1405 return getOpcode() == TargetOpcode::PHI ||
1406 getOpcode() == TargetOpcode::G_PHI;
1407 }
1411 return getOpcode() == TargetOpcode::INLINEASM ||
1412 getOpcode() == TargetOpcode::INLINEASM_BR;
1413 }
1414
1415
1416
1418
1421
1423 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1424 }
1425
1427 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1428 }
1429
1431 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1432 }
1433
1435 return getOpcode() == TargetOpcode::BUNDLE;
1436 }
1437
1439 return getOpcode() == TargetOpcode::COPY;
1440 }
1441
1444 }
1445
1447 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1448 }
1449
1451
1452
1453
1456 }
1457
1458
1462 }
1463
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1466
1469 default:
1471
1472 case TargetOpcode::PHI:
1473 case TargetOpcode::G_PHI:
1474 case TargetOpcode::COPY:
1475 case TargetOpcode::INSERT_SUBREG:
1476 case TargetOpcode::SUBREG_TO_REG:
1477 case TargetOpcode::REG_SEQUENCE:
1478 return true;
1479 }
1480 }
1481
1482
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1493
1496 }
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1503 }
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1516 }
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1524 }
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1531 }
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1538 }
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1546
1548 bool isKill = false) const;
1549
1550
1551
1554 bool isKill = false) {
1557 }
1558
1561 bool isKill = false) const {
1564 }
1565
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1571
1573 bool isDead = false,
1574 bool Overlap = false) const;
1575
1576
1577
1580 bool isDead = false,
1581 bool Overlap = false) {
1584 }
1585
1588 bool isDead = false,
1589 bool Overlap = false) const {
1592 }
1593
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1605 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
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1633 bool ExploreBundle = false) const;
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1655 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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1667 unsigned *UseOpIdx = nullptr) const {
1670 return false;
1671 if (UseOpIdx)
1673 return true;
1674 }
1675
1676
1677
1678
1680 unsigned *DefOpIdx = nullptr) const {
1683 return false;
1684 if (DefOpIdx)
1686 return true;
1687 }
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1700
1703 bool AddIfNotFound = false);
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1714 bool AddIfNotFound = false);
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1799 std::optional
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1806 std::optional
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1833 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1834 bool SkipDebugLoc = false, bool AddNewLine = true,
1837 bool SkipOpers = false, bool SkipDebugLoc = false,
1838 bool AddNewLine = true,
1840 void dump() const;
1841
1842
1844 unsigned MaxDepth = UINT_MAX) const;
1845
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1879 DbgLoc = std::move(DL);
1880 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1881 }
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1971 MO.TiedTo = 0;
1972 }
1973 }
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1991 if (MO.isReg()) {
1992 MO.setReg(0);
1993 MO.setSubReg(0);
1994 }
1995 }
1996 }
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2000 }
2001
2002 std::tuple<Register, Register, Register> getFirst3Regs() const {
2005 }
2006
2007 std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
2010 }
2011
2012 std::tuple<Register, Register, Register, Register, Register>
2017 }
2018
2020 std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
2021 std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
2022 std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
2023
2024 std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
2025 std::tuple<Register, LLT, Register, LLT, Register, LLT>
2027 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2032
2033private:
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2064 MDNode *HeapAllocMarker, MDNode *PCSections,
2066};
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2074 return nullptr;
2075 }
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2090};
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2097 return OS;
2098}
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2100}
2101
2102#endif
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines DenseMapInfo traits for DenseMap.
const HexagonInstrInfo * TII
mir Rename Register Operands
#define LLVM_MI_ASMPRINTERFLAGS_BITS
#define LLVM_MI_FLAGS_BITS
#define LLVM_MI_NUMOPERANDS_BITS
unsigned const TargetRegisterInfo * TRI
Promote Memory to Register
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This header defines support for implementing classes that have some trailing object (or arrays of obj...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
Describe properties that are true of each instruction in the target description file.
uint64_t getFlags() const
Return flags of this instruction.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Representation of each machine instruction.
mop_iterator operands_begin()
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
std::tuple< Register, Register, Register, Register, Register > getFirst5Regs() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
bool isReturn(QueryType Type=AnyInBundle) const
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
bool isDebugValueList() const
iterator_range< mop_iterator > explicit_uses()
void bundleWithPred()
Bundle this instruction with its predecessor.
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
std::tuple< Register, Register, Register, Register > getFirst4Regs() const
bool isImplicitDef() const
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands which may be register uses.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
const MachineBasicBlock * getParent() const
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
MDNode * getMMRAMetadata() const
Helper to extract mmra.op metadata.
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool isDebugOffsetImm() const
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
MachineFunction * getMF()
QueryType
API for querying MachineInstr properties.
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
MachineBasicBlock * getParent()
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
bool isCall(QueryType Type=AnyInBundle) const
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Register isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands which may be register uses.
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
iterator_range< const_mop_iterator > explicit_uses() const
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isSafeToMove(bool &SawStore) const
Return true if it is safe to move this instruction.
iterator_range< filtered_mop_iterator > all_uses()
Returns an iterator range over all operands that are (explicit or implicit) register uses.
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
unsigned getNumOperands() const
Retuns the total number of operands.
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< const_mop_iterator > explicit_operands() const
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
const MachineOperand * const_mop_iterator
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
bool isAnnotationLabel() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
MachineOperand & getDebugOffset()
iterator_range< mop_iterator > explicit_operands()
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSubregToReg() const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool wouldBeTriviallyDead() const
Return true if this instruction would be trivially dead if all of its defined registers were dead.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
MachineOperand & getOperand(unsigned i)
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const_mop_iterator operands_end() const
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
bool isDebugOrPseudoInstr() const
bool isStackAligningInlineAsm() const
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
mop_iterator operands_end()
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void clearFlags(unsigned flags)
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
iterator_range< filtered_const_mop_iterator > all_uses() const
Returns an iterator range over all operands that are (explicit or implicit) register uses.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
MachineInstr & operator=(const MachineInstr &)=delete
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
bool isCandidateForAdditionalCallInfo(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an additional information associated with it.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr kills the specified register.
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
bool isRegSequence() const
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const
Returns true if the register is dead in this machine instruction.
const_mop_iterator operands_begin() const
static uint32_t copyFlagsFromInstruction(const Instruction &I)
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr fully defines the specified register.
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
const MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
bool isJumpTableDebugInfo() const
std::tuple< Register, Register, Register > getFirst3Regs() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
iterator_range< mop_iterator > operands()
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isInsertSubreg() const
iterator_range< filtered_const_mop_iterator > all_defs() const
Returns an iterator range over all operands that are (explicit or implicit) register defs.
bool isLifetimeMarker() const
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void emitGenericError(const Twine &ErrMsg) const
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
iterator_range< const_mop_iterator > operands() const
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
bool isLabel() const
Returns true if the MachineInstr represents a label.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isExtractSubreg() const
bool isNonListDebugValue() const
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
iterator_range< const_mop_iterator > implicit_operands() const
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
bool isDebugValue() const
unsigned getDebugOperandIndex(const MachineOperand *Op) const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
MachineOperand & getDebugOperand(unsigned Index)
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
bool isDebugOperand(const MachineOperand *Op) const
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
void emitInlineAsmError(const Twine &ErrMsg) const
Emit an error referring to the source location of this instruction.
uint32_t getFlags() const
Return the MI flags bitvector.
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool shouldUpdateAdditionalCallInfo() const
Return true if copying, moving, or erasing this instruction requires updating additional call info (s...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
const MachineOperand & getDebugOperand(unsigned Index) const
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineInstr(const MachineInstr &)=delete
const MDNode * getLocCookieMD() const
For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.
const MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isBundled() const
Return true if this instruction part of a bundle.
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
std::tuple< Register, Register > getFirst2Regs() const
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Manage lifetime of a slot tracker for printing IR.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Wrapper class representing virtual and physical registers.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
Specialization of filter_iterator_base for forward iteration only.
An ilist node that can access its parent list.
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
This file defines classes to implement an intrusive doubly linked list class (i.e.
This file defines the ilist_node class template, which is a convenient base class for creating classe...
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
This is an optimization pass for GlobalISel generic memory operations.
constexpr auto adl_begin(RangeT &&range) -> decltype(adl_detail::begin_impl(std::forward< RangeT >(range)))
Returns the begin iterator to range using std::begin and function found through Argument-Dependent Lo...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
constexpr auto adl_end(RangeT &&range) -> decltype(adl_detail::end_impl(std::forward< RangeT >(range)))
Returns the end iterator to range using std::end and functions found through Argument-Dependent Looku...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
ArrayRef(const T &OneElt) -> ArrayRef< T >
An information struct used to provide DenseMap with the various necessary components for a given valu...
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
static MachineInstr * getEmptyKey()
static unsigned getHashValue(const MachineInstr *const &MI)
static MachineInstr * getTombstoneKey()
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Callbacks do nothing by default in iplist and ilist.
Template traits for intrusive list.