MachineInstrBundle.cpp Source File (original) (raw)

22#include

23using namespace llvm;

25namespace {

27 public:

28 static char ID;

29 UnpackMachineBundles(

30 std::function<bool(const MachineFunction &)> Ftor = nullptr)

31 : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {

33 }

35 bool runOnMachineFunction(MachineFunction &MF) override;

37 private:

38 std::function<bool(const MachineFunction &)> PredicateFtor;

39 };

40}

42char UnpackMachineBundles::ID = 0;

45 "Unpack machine instruction bundles", false, false)

48 if (PredicateFtor && !PredicateFtor(MF))

49 return false;

54 MIE = MBB.instr_end(); MII != MIE; ) {

59 if (MI->isBundle()) {

60 while (++MII != MIE && MII->isBundledWithPred()) {

61 MII->unbundleFromPred();

63 if (MO.isReg() && MO.isInternalRead())

64 MO.setIsInternalRead(false);

65 }

66 }

67 MI->eraseFromParent();

70 continue;

71 }

73 ++MII;

74 }

75 }

78}

83 return new UnpackMachineBundles(std::move(Ftor));

84}

93 for (auto MII = FirstMI; MII != LastMI; ++MII) {

94 if (DebugLoc MIIDL = MII->getDebugLoc()) {

95 if (MIIDL.getLine() != 0)

96 return MIIDL;

97 DL = MIIDL.get();

98 }

99 }

100 return DL;

101}

102

103

104

105

109 if (Reg.isPhysical()) {

110 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))

111 if (!LocalDefsP[static_cast<unsigned>(Unit)])

112 return false;

113

114 return true;

115 }

117}

118

119

120

121

122

123

124

128 assert(FirstMI != LastMI && "Empty bundle?");

130

134

138

147 for (auto MII = FirstMI; MII != LastMI; ++MII) {

148

149 if (MII->isDebugInstr())

150 continue;

151

154 if (!Reg)

155 continue;

156

158 MO.setIsInternalRead();

159 if (MO.isKill()) {

160

161 DeadDefSet.insert(Reg);

162 }

163 } else {

164 if (ExternUses.insert(Reg)) {

165 if (MO.isUndef())

166 UndefUseSet.insert(Reg);

167 }

168 if (MO.isKill()) {

169

170 KilledUseSet.insert(Reg);

171 }

172 if (MO.isTied() && Reg.isVirtual()) {

173

174

175

176 unsigned TiedIdx = MII->findTiedOperandIdx(MO.getOperandNo());

180 }

181 }

182 }

183

186 if (!Reg)

187 continue;

188

189 if (LocalDefs.insert(Reg)) {

190 if (!MO.isDead() && Reg.isPhysical()) {

191 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))

192 LocalDefsP.set(static_cast<unsigned>(Unit));

193 }

194 } else {

195 if (!MO.isDead()) {

196

197 DeadDefSet.erase(Reg);

198 }

199 }

200 if (MO.isDead())

201 DeadDefSet.insert(Reg);

202 }

203

204

205

210

211 if (MII->mayLoadOrStore())

213 }

214

215 for (Register Reg : LocalDefs) {

216

220 }

221

222 for (Register Reg : ExternUses) {

223 bool isKill = KilledUseSet.contains(Reg);

227 }

228

229 for (auto [DefReg, UseReg] : TiedOperands) {

230 unsigned DefIdx =

231 std::distance(LocalDefs.begin(), llvm::find(LocalDefs, DefReg));

232 unsigned UseIdx =

237 }

238

240}

241

242

243

244

245

246

252 while (LastMI != E && LastMI->isInsideBundle())

253 ++LastMI;

255 return LastMI;

256}

257

258

259

265 if (MII == MIE)

266 continue;

267 assert(!MII->isInsideBundle() &&

268 "First instr cannot be inside bundle before finalization!");

269

270 for (++MII; MII != MIE; ) {

271 if (!MII->isInsideBundle())

272 ++MII;

273 else {

276 }

277 }

278 }

279

281}

282

290 continue;

291

292

294 Ops->push_back(std::make_pair(MO.getParent(), O.getOperandNo()));

295

296

300 RI.Tied = true;

301 }

302

303

306 else if (!RI.Tied &&

308 RI.Tied = true;

309 }

310 return RI;

311}

312

313std::pair<LaneBitmask, LaneBitmask>

317

319

321 if (!MO.isReg() || MO.getReg() != Reg)

322 continue;

323

324 unsigned SubReg = MO.getSubReg();

325 if (SubReg == 0 && MO.isUse() && !MO.isUndef())

326 UseMask |= MRI.getMaxLaneMaskForVReg(Reg);

327

329 if (MO.isDef()) {

330 if (!MO.isUndef())

331 UseMask |= ~SubRegMask;

332 DefMask |= SubRegMask;

333 } else if (!MO.isUndef())

334 UseMask |= SubRegMask;

335 }

336

337 return {UseMask, DefMask};

338}

339

342 bool AllDefsDead = true;

343 PhysRegInfo PRI = {false, false, false, false, false, false, false, false};

344

345 assert(Reg.isPhysical() && "analyzePhysReg not given a physical register!");

347 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {

349 continue;

350 }

351

352 if (!MO.isReg())

353 continue;

354

355 Register MOReg = MO.getReg();

357 continue;

358

359 if ( TRI ->regsOverlap(MOReg, Reg))

360 continue;

361

362 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);

363 if (MO.readsReg()) {

364 PRI.Read = true;

365 if (Covered) {

367 if (MO.isKill())

369 }

370 } else if (MO.isDef()) {

372 if (Covered)

374 if (!MO.isDead())

375 AllDefsDead = false;

376 }

377 }

378

379 if (AllDefsDead) {

384 }

385

386 return PRI;

387}

388

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static Register UseReg(const MachineOperand &MO)

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static bool containsReg(SmallSetVector< Register, 32 > LocalDefsV, const BitVector &LocalDefsP, Register Reg, const TargetRegisterInfo *TRI)

Check if target reg is contained in given lists, which are: LocalDefsV as given list for virtual regs...

Definition MachineInstrBundle.cpp:106

static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)

Return the first DebugLoc that has line number information, given a range of instructions.

Definition MachineInstrBundle.cpp:90

static bool isUndef(const MachineInstr &MI)

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)

This file implements a set that has insertion order iteration characteristics.

This file defines the SmallSet class.

This file defines the SmallVector class.

LLVM_ABI PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition MachineInstrBundle.cpp:390

FunctionPass class - This class is used to implement most global optimizations.

Helper class for constructing bundles of MachineInstrs.

MIBundleBuilder & prepend(MachineInstr *MI)

Insert MI into MBB by prepending it to the instructions in the bundle.

MIBundleOperands - Iterate over all operands in a bundle of machine instructions.

Instructions::iterator instr_iterator

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const

Return true if the use operand of the specified index is tied to a def operand.

LLVM_ABI void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)

Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...

LLVM_ABI void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

MachineOperand class - Representation of each machine instruction operand.

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses none()

Convenience factory function for the empty preserved set.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

size_type size() const

Determine the number of elements in the SetVector.

bool contains(const_arg_type key) const

Check if the SetVector contains the given key.

iterator begin()

Get an iterator to the beginning of the SetVector.

bool insert(const value_type &X)

Insert a new element into the SetVector.

A SetVector that performs no allocations if smaller than a certain size.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

bool contains(const T &V) const

Check if the SmallSet contains the given element.

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

reference emplace_back(ArgTypes &&... Args)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)

finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...

Definition MachineInstrBundle.cpp:125

auto find(R &&Range, const T &Val)

Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI bool finalizeBundles(MachineFunction &MF)

finalizeBundles - Finalize instruction bundles in the specified MachineFunction.

Definition MachineInstrBundle.cpp:260

LLVM_ABI PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI)

AnalyzePhysRegInBundle - Analyze how the current instruction or bundle uses a physical register.

Definition MachineInstrBundle.cpp:340

unsigned getDeadRegState(bool B)

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

unsigned getImplRegState(bool B)

iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)

LLVM_ABI VirtRegInfo AnalyzeVirtRegInBundle(MachineInstr &MI, Register Reg, SmallVectorImpl< std::pair< MachineInstr *, unsigned > > *Ops=nullptr)

AnalyzeVirtRegInBundle - Analyze how the current instruction or bundle uses a virtual register.

Definition MachineInstrBundle.cpp:283

unsigned getUndefRegState(bool B)

unsigned getDefRegState(bool B)

unsigned getKillRegState(bool B)

LLVM_ABI FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)

Definition MachineInstrBundle.cpp:81

OutputIt move(R &&Range, OutputIt Out)

Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI void initializeUnpackMachineBundlesPass(PassRegistry &)

LLVM_ABI char & UnpackMachineBundlesID

UnpackMachineBundles - This pass unpack machine instruction bundles.

Definition MachineInstrBundle.cpp:43

LLVM_ABI std::pair< LaneBitmask, LaneBitmask > AnalyzeVirtRegLanesInBundle(const MachineInstr &MI, Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)

Return a pair of lane masks (reads, writes) indicating which lanes this instruction uses with Reg.

Definition MachineInstrBundle.cpp:314

Information about how a physical register Reg is used by a set of operands.

bool Read

Reg or one of its aliases is read.

bool Defined

Reg or one of its aliases is defined.

bool Killed

There is a use operand of reg or a super-register with kill flag set.

bool PartialDeadDef

Reg is Defined and all defs of reg or an overlapping register are dead.

bool Clobbered

There is a regmask operand indicating Reg is clobbered.

bool FullyRead

Reg or a super-register is read. The full register is read.

bool FullyDefined

Reg or a super-register is defined.

VirtRegInfo - Information about a virtual register used by a set of operands.

bool Reads

Reads - One of the operands read the virtual register.

bool Tied

Tied - Uses and defs must use the same register.

bool Writes

Writes - One of the operands writes the virtual register.