MachineOperand.cpp Source File (original) (raw)

24#include "llvm/Config/llvm-config.h"

32#include

34using namespace llvm;

38 cl::desc("Number of registers to limit to when "

39 "printing regmask operands in IR dumps. "

40 "unlimited = -1"),

47 return MF;

48 return nullptr;

49}

54}

57 assert(getParent() && "Operand does not belong to any instruction!");

59}

63 return;

66 IsRenamable = false;

73 MRI.removeRegOperandFromUseList(this);

74 SmallContents.RegNo = Reg;

75 MRI.addRegOperandToUseList(this);

76 return;

77 }

80 SmallContents.RegNo = Reg;

81}

85 assert(Reg.isVirtual());

87 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());

89 if (SubIdx)

91}

94 assert(Reg.isPhysical());

102 }

104}

105

106

108 assert(isReg() && "Wrong MachineOperand accessor");

109 assert((!Val || isDebug ()) && "Marking a debug operation as def");

110 if (IsDef == Val)

111 return;

112 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");

113

116 MRI.removeRegOperandFromUseList(this);

117 IsDef = Val;

118 MRI.addRegOperandToUseList(this);

119 return;

120 }

121 IsDef = Val;

122}

123

125 assert(isReg() && "Wrong MachineOperand accessor");

127 "isRenamable should only be checked on physical registers");

128 if (!IsRenamable)

129 return false;

130

132 if ()

133 return true;

134

137

138 assert(isUse() && "Reg is not def or use");

140}

141

143 assert(isReg() && "Wrong MachineOperand accessor");

145 "setIsRenamable should only be called on physical registers");

146 IsRenamable = Val;

147}

148

149

150

151void MachineOperand::removeRegFromUses() {

152 if ( isReg () || !isOnRegUseList())

153 return;

154

156 MF->getRegInfo().removeRegOperandFromUseList(this);

157}

158

159

160

161

163 assert(( isReg () || isTied ()) && "Cannot change a tied operand into an imm");

164

165 removeRegFromUses();

166

168 Contents.ImmVal = ImmVal;

170}

171

173 unsigned TargetFlags) {

174 assert(( isReg () || isTied ()) && "Cannot change a tied operand into an imm");

175

176 removeRegFromUses();

177

179 Contents.CFP = FPImm;

181}

182

184 unsigned TargetFlags) {

186 "Cannot change a tied operand into an external symbol");

187

188 removeRegFromUses();

189

191 Contents.OffsetedInfo.Val.SymbolName = SymName;

192 setOffset(0);

194}

195

197 unsigned TargetFlags) {

199 "Cannot change a tied operand into a global address");

200

201 removeRegFromUses();

202

204 Contents.OffsetedInfo.Val.GV = GV;

207}

208

210 unsigned TargetFlags) {

212 "Cannot change a tied operand into a block address");

213

214 removeRegFromUses();

215

217 Contents.OffsetedInfo.Val.BA = BA;

220}

221

224 "Cannot change a tied operand into an MCSymbol");

225

226 removeRegFromUses();

227

229 Contents.Sym = Sym;

231}

232

235 "Cannot change a tied operand into a FrameIndex");

236

237 removeRegFromUses();

238

242}

243

245 unsigned TargetFlags) {

247 "Cannot change a tied operand into a FrameIndex");

248

249 removeRegFromUses();

250

255}

256

258 unsigned TargetFlags) {

260 "Cannot change a tied operand into a DbgInstrRef");

261

262 removeRegFromUses();

263

268}

269

270

271

272

278 RegInfo = &MF->getRegInfo();

279

280

281 bool WasReg = isReg();

282 if (RegInfo && WasReg)

284

285

287 if ( isDef && MI && MI->isDebugInstr())

289

290

294 SmallContents.RegNo = Reg;

295 SubReg_TargetFlags = 0;

297 IsImp = isImp;

299 IsRenamable = false;

301 IsInternalRead = false;

302 IsEarlyClobber = false;

304

305 Contents.Reg.Prev = nullptr;

306

307 if (!WasReg)

308 TiedTo = 0;

309

310

311

312 if (RegInfo)

314}

315

316

317

318

322 return false;

323

353

355 const uint32_t *OtherRegMask = Other.getRegMask();

356 if (RegMask == OtherRegMask)

357 return true;

358

362

363 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);

364 }

365

366

367 return false;

368 }

384 }

386}

387

388

392

425 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);

428 }

429

430 assert(0 && "MachineOperand not associated with any MachineFunction");

432 }

448 }

450}

451

452

453

458 TRI = MF->getSubtarget().getRegisterInfo();

459 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();

460 }

461}

462

465 assert(TII && "expected instruction info");

466 auto Indices = TII->getSerializableTargetIndices();

467 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {

468 return I.first == Index;

469 });

470 if (Found != Indices.end())

471 return Found->second;

472 return nullptr;

473}

474

478}

479

482 for (const auto &I : Flags) {

483 if (I.first == TF) {

484 return I.second;

485 }

486 }

487 return nullptr;

488}

489

492 if ( TRI ) {

493 OS << "%dwarfreg." << DwarfReg;

494 return;

495 }

496

497 if (std::optional Reg = TRI->getLLVMRegNum(DwarfReg, true))

499 else

500 OS << "";

501}

502

505 OS << "%ir-block.";

508 return;

509 }

510 std::optional Slot;

514 } else if (const Module *M = F->getParent()) {

515 ModuleSlotTracker CustomMST(M, false);

518 }

519 }

520 if (Slot)

522 else

523 OS << "";

524}

525

529 switch (SSID) {

531 break;

532 default:

533 if (SSNs.empty())

535

536 OS << "syncscope(\"";

537 printEscapedString(SSNs[SSID], OS);

538 OS << "\") ";

539 break;

540 }

541}

542

544 unsigned TMMOFlag) {

545 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();

546 for (const auto &I : Flags) {

547 if (I.first == TMMOFlag) {

548 return I.second;

549 }

550 }

551 return nullptr;

552}

553

557 if (MFI) {

560 if (Alloca->hasName())

561 Name = Alloca->getName();

562 if (IsFixed)

564 }

566}

567

570 OS << "%subreg.";

571 if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())

572 OS << TRI->getSubRegIndexName(Index);

573 else

574 OS << Index;

575}

576

579 if (.getTargetFlags())

580 return;

582 if (!MF)

583 return;

584

586 assert(TII && "expected instruction info");

588 OS << "target-flags(";

589 const bool HasDirectFlags = Flags.first;

590 const bool HasBitmaskFlags = Flags.second;

591 if (!HasDirectFlags && !HasBitmaskFlags) {

592 OS << ") ";

593 return;

594 }

595 if (HasDirectFlags) {

598 else

599 OS << "";

600 }

601 if (!HasBitmaskFlags) {

602 OS << ") ";

603 return;

604 }

605 bool IsCommaNeeded = HasDirectFlags;

606 unsigned BitMask = Flags.second;

608 for (const auto &Mask : BitMasks) {

609

610 if ((BitMask & Mask.first) == Mask.first) {

611 if (IsCommaNeeded)

612 OS << ", ";

613 IsCommaNeeded = true;

614 OS << Mask.second;

615

616 BitMask &= ~(Mask.first);

617 }

618 }

619 if (BitMask) {

620

621

622 if (IsCommaNeeded)

623 OS << ", ";

624 OS << "";

625 }

626 OS << ") ";

627}

628

630 OS << "<mcsymbol " << Sym << ">";

631}

632

634 unsigned FrameIndex,

636 if (IsFixed) {

637 OS << "%fixed-stack." << FrameIndex;

638 return;

639 }

640

641 OS << "%stack." << FrameIndex;

642 if ( Name .empty())

644}

645

648 return;

651 return;

652 }

654}

655

657 if (Slot == -1)

658 OS << "";

659 else

660 OS << Slot;

661}

662

667 OS << "same_value ";

671 break;

673 OS << "remember_state ";

676 break;

678 OS << "restore_state ";

681 break;

683 OS << "offset ";

688 break;

690 OS << "def_cfa_register ";

694 break;

696 OS << "def_cfa_offset ";

700 break;

702 OS << "def_cfa ";

707 break;

709 OS << "llvm_def_aspace_cfa ";

715 break;

717 OS << "rel_offset ";

722 break;

724 OS << "adjust_cfa_offset ";

728 break;

730 OS << "restore ";

734 break;

736 OS << "escape ";

741 for (size_t i = 0; i < e; ++i)

744 }

745 break;

746 }

748 OS << "undefined ";

752 break;

754 OS << "register ";

758 OS << ", ";

760 break;

762 OS << "window_save ";

765 break;

767 OS << "negate_ra_sign_state ";

770 break;

772 OS << "negate_ra_sign_state_with_pc ";

775 break;

776 default:

777

778 OS << "";

779 break;

780 }

781}

782

786}

787

793 print(OS, DummyMST, TypeToPrint, std::nullopt, false,

794 true,

795 true,

796 0, TRI, IntrinsicInfo);

797}

798

800 LLT TypeToPrint, std::optional OpIdx,

801 bool PrintDef, bool IsStandalone,

802 bool ShouldPrintRegisterTies,

803 unsigned TiedOperandIdx,

811 OS << (isDef() ? "implicit-def " : "implicit ");

812 else if (PrintDef && isDef())

813

814 OS << "def ";

816 OS << "internal ";

818 OS << "dead ";

820 OS << "killed ";

822 OS << "undef ";

824 OS << "early-clobber ";

826 OS << "renamable ";

827

828

829

831 if (Reg.isVirtual()) {

833 MRI = &MF->getRegInfo();

834 }

835 }

836

838

841 OS << '.' << TRI->getSubRegIndexName(SubReg);

842 else

844 }

845

846 if (Reg.isVirtual()) {

849 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {

850 OS << ':';

852 }

853 }

854 }

855

856 if (ShouldPrintRegisterTies && isTied() && isDef ())

857 OS << "(tied-def " << TiedOperandIdx << ")";

858

859 if (TypeToPrint.isValid())

860 OS << '(' << TypeToPrint << ')';

861 break;

862 }

866 const auto *TII = MF->getSubtarget().getInstrInfo();

867 assert(TII && "expected instruction info");

868 Formatter = TII->getMIRFormatter();

869 }

870 if (Formatter)

872 else

874 break;

875 }

878 break;

881 break;

884 break;

887 bool IsFixed = false;

890 MFI = &MF->getFrameInfo();

892 break;

893 }

897 break;

899 OS << "target-index(";

900 const char *Name = "";

903 Name = TargetIndexName;

906 break;

907 }

910 break;

913 GV->printAsOperand(OS, false, MST);

914 else

915 OS << "globaladdress(null)";

916

918 break;

921 OS << '&';

922 if (Name.empty()) {

923 OS << "\"\"";

924 } else {

926 }

928 break;

929 }

931 OS << "blockaddress(";

933 MST);

934 OS << ", ";

936 OS << ')';

938 break;

939 }

941 OS << "<regmask";

942 if (TRI) {

943 unsigned NumRegsInMask = 0;

944 unsigned NumRegsEmitted = 0;

945 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {

946 unsigned MaskWord = i / 32;

947 unsigned MaskBit = i % 32;

948 if (getRegMask()[MaskWord] & (1 << MaskBit)) {

952 NumRegsEmitted++;

953 }

954 NumRegsInMask++;

955 }

956 }

957 if (NumRegsEmitted != NumRegsInMask)

958 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";

959 } else {

960 OS << " ...";

961 }

962 OS << ">";

963 break;

964 }

967 OS << "liveout(";

968 if ( TRI ) {

969 OS << "";

970 } else {

971 bool IsCommaNeeded = false;

972 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {

973 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {

974 if (IsCommaNeeded)

975 OS << ", ";

977 IsCommaNeeded = true;

978 }

979 }

980 }

981 OS << ")";

982 break;

983 }

986 break;

989 break;

993 break;

994 }

998 else

999 OS << "";

1000 break;

1001 }

1004 if (ID < Intrinsic::num_intrinsics)

1006 else if (IntrinsicInfo)

1007 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';

1008 else

1009 OS << "intrinsic(" << ID << ')';

1010 break;

1011 }

1015 << Pred << ')';

1016 break;

1017 }

1019 OS << "shufflemask(";

1022 for (int Elt : Mask) {

1023 if (Elt == -1)

1024 OS << Separator << "undef";

1025 else

1026 OS << Separator << Elt;

1027 Separator = ", ";

1028 }

1029

1030 OS << ')';

1031 break;

1032 }

1033}

1034

1035#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

1037#endif

1038

1039

1040

1041

1042

1043

1044

1046

1047

1048

1051 if (!isa<const Value *>(V))

1052 return false;

1053

1054 const Value *BasePtr = cast<const Value *>(V);

1055 if (BasePtr == nullptr)

1056 return false;

1057

1060 dyn_cast(BasePtr));

1061}

1062

1063

1064

1067}

1068

1069

1070

1072 int FI, int64_t Offset) {

1074}

1075

1078}

1079

1082}

1083

1087}

1088

1091}

1092

1098 : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),

1099 AAInfo(AAInfo), Ranges(Ranges) {

1100 assert((PtrInfo.V.isNull() || isa<const PseudoSourceValue *>(PtrInfo.V) ||

1101 isa(cast<const Value *>(PtrInfo.V)->getType())) &&

1102 "invalid pointer value");

1104

1105 AtomicInfo.SSID = static_cast<unsigned>(SSID);

1107 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);

1109 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);

1111}

1112

1120 ptrinfo, F,

1121 !TS.hasValue() ? LLT()

1122 : TS.isScalable()

1123 ? LLT::scalable_vector(1, 8 * TS.getValue().getKnownMinValue())

1124 : LLT::scalar(8 * TS.getValue().getKnownMinValue()),

1125 BaseAlignment, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}

1126

1128

1129

1133 "Size mismatch!");

1135

1137

1138

1139 PtrInfo = MMO->PtrInfo;

1140 }

1141}

1142

1143

1144

1147}

1148

1154 OS << '(';

1156 OS << "volatile ";

1158 OS << "non-temporal ";

1160 OS << "dereferenceable ";

1162 OS << "invariant ";

1163 if (TII) {

1166 << "\" ";

1169 << "\" ";

1172 << "\" ";

1175 << "\" ";

1176 } else {

1178 OS << "\"MOTargetFlag1\" ";

1180 OS << "\"MOTargetFlag2\" ";

1182 OS << "\"MOTargetFlag3\" ";

1184 OS << "\"MOTargetFlag4\" ";

1185 }

1186

1188 "machine memory operand must be a load or store (or both)");

1190 OS << "load ";

1192 OS << "store ";

1193

1195

1200

1203 else

1204 OS << "unknown-size";

1205

1211 assert(PVal && "Expected a pseudo source value");

1212 switch (PVal->kind()) {

1214 OS << "stack";

1215 break;

1217 OS << "got";

1218 break;

1220 OS << "jump-table";

1221 break;

1223 OS << "constant-pool";

1224 break;

1226 int FrameIndex = cast(PVal)->getFrameIndex();

1227 bool IsFixed = true;

1229 break;

1230 }

1232 OS << "call-entry ";

1233 cast(PVal)->getValue()->printAsOperand(

1234 OS, false, MST);

1235 break;

1237 OS << "call-entry &";

1239 OS, cast(PVal)->getSymbol());

1240 break;

1241 default: {

1243

1244

1245

1246

1247 OS << "custom \"";

1249 OS << '\"';

1250 break;

1251 }

1252 }

1255 : isLoad() ? " from "

1256 : " into ")

1257 << "unknown-address";

1258 }

1260 if ( getSize ().hasValue() ||

1267 if (AAInfo.TBAA) {

1268 OS << ", !tbaa ";

1270 }

1271 if (AAInfo.Scope) {

1272 OS << ", !alias.scope ";

1274 }

1276 OS << ", !noalias ";

1278 }

1280 OS << ", !range ";

1282 }

1283

1284

1286 OS << ", addrspace " << AS;

1287

1288 OS << ')';

1289}

unsigned const MachineRegisterInfo * MRI

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

This file contains the declarations for the subclasses of Constant, which represent the different fla...

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

const HexagonInstrInfo * TII

static bool isUndef(ArrayRef< int > Mask)

This file contains an interface for creating legacy passes to print out IR in various granularities.

static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)

static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)

static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)

static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)

static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)

static const char * getTargetIndexName(const MachineFunction &MF, int Index)

static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)

static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)

static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)

static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)

static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)

static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)

static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)

unsigned const TargetRegisterInfo * TRI

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)

Class for arbitrary precision integers.

an instruction to allocate memory on the stack

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

LLVM Basic Block Representation.

const Function * getParent() const

Return the enclosing method, or null if none.

The address of a basic block.

Function * getFunction() const

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

bool isIntPredicate() const

ConstantFP - Floating Point Values [float, double].

This class represents an Operation in the Expression.

A parsed version of the target data layout string in and methods for querying it.

unsigned getAllocaAddrSpace() const

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

Decompose the machine operand's target flags into two values - the direct target flag value and any o...

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

Return an array that contains the direct target flag values and their names.

ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override

Return an array that contains the bitmask target flag values and their names.

constexpr bool isValid() const

This is an important class for using LLVM in a threaded context.

void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const

getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...

MCSymbol * getLabel() const

unsigned getAddressSpace() const

unsigned getRegister2() const

unsigned getRegister() const

OpType getOperation() const

StringRef getValues() const

int64_t getOffset() const

Wrapper class representing physical registers. Should be passed by value.

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

MIRFormater - Interface to format MIR operand based on target.

virtual void printImm(raw_ostream &OS, const MachineInstr &MI, std::optional< unsigned > OpIdx, int64_t Imm) const

Implement target specific printing for machine operand immediate value, so that we can have more mean...

virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const

Implement target specific printing of target custom pseudo source value.

static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)

Helper functions to print IR value as MIR serialization format which will be useful for target specif...

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

const AllocaInst * getObjectAllocation(int ObjectIdx) const

Return the underlying Alloca of the specified stack object if it exists.

bool isFixedObjectIndex(int ObjectIdx) const

Returns true if the specified index corresponds to a fixed stack object.

int getObjectIndexBegin() const

Return the minimum frame object index.

PseudoSourceValueManager & getPSVManager() const

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Representation of each machine instruction.

unsigned getOperandNo(const_mop_iterator I) const

Returns the number of the operand iterator I points to.

A description of a memory reference used in the backend.

LocationSize getSize() const

Return the size in bytes of the memory reference.

AtomicOrdering getFailureOrdering() const

For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.

const PseudoSourceValue * getPseudoValue() const

LLT getMemoryType() const

Return the memory type of the memory reference.

unsigned getAddrSpace() const

void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const

Support for operator<<.

bool isNonTemporal() const

const MDNode * getRanges() const

Return the range tag for the memory reference.

void refineAlignment(const MachineMemOperand *MMO)

Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.

SyncScope::ID getSyncScopeID() const

Returns the synchronization scope ID for this memory operation.

const void * getOpaqueValue() const

MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LocationSize TS, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.

Flags

Flags values. These may be or'd together.

AtomicOrdering getSuccessOrdering() const

Return the atomic ordering requirements for this memory operation.

Flags getFlags() const

Return the raw flags of the source value,.

Align getAlign() const

Return the minimum known alignment in bytes of the actual memory reference.

bool isDereferenceable() const

AAMDNodes getAAInfo() const

Return the AA tags for the memory reference.

const Value * getValue() const

Return the base address of the memory access.

Align getBaseAlign() const

Return the minimum known alignment in bytes of the base address, without the offset.

int64_t getOffset() const

For normal values, this is a byte offset added to the base address.

MachineOperand class - Representation of each machine instruction operand.

void setSubReg(unsigned subReg)

unsigned getSubReg() const

unsigned getInstrRefOpIndex() const

void setInstrRefInstrIndex(unsigned InstrIdx)

unsigned getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

const GlobalValue * getGlobal() const

void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)

Replace this operand with a frame index.

const uint32_t * getRegLiveOut() const

getRegLiveOut - Returns a bit mask of live-out registers.

void setInstrRefOpIndex(unsigned OpIdx)

const ConstantInt * getCImm() const

const char * getTargetIndexName() const

getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...

static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)

Print a stack object reference.

static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)

Print a subreg index operand.

unsigned getInstrRefInstrIndex() const

static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)

Print operand target flags.

void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)

ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.

void setIsRenamable(bool Val=true)

bool isReg() const

isReg - Tests if this is a MO_Register operand.

const MDNode * getMetadata() const

MachineBasicBlock * getMBB() const

ArrayRef< int > getShuffleMask() const

void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)

ChangeToMCSymbol - Replace this operand with a new MC symbol operand.

void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)

Replace this operand with a target index.

void setReg(Register Reg)

Change the register this operand corresponds to.

void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

void ChangeToES(const char *SymName, unsigned TargetFlags=0)

ChangeToES - Replace this operand with a new external symbol operand.

void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)

ChangeToGA - Replace this operand with a new global address operand.

unsigned getCFIIndex() const

bool isRenamable() const

isRenamable - Returns true if this register may be renamed, i.e.

void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)

ChangeToBA - Replace this operand with a new block address operand.

static void printOperandOffset(raw_ostream &OS, int64_t Offset)

Print the offset with explicit +/- signs.

void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)

Replace this operand with an Instruction Reference.

void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)

ChangeToRegister - Replace this operand with a new register operand of the specified value.

const BlockAddress * getBlockAddress() const

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...

static unsigned getRegMaskSize(unsigned NumRegs)

Returns number of elements needed for a regmask array.

void setOffset(int64_t Offset)

static void printIRSlotNumber(raw_ostream &OS, int Slot)

Print an IRSlotNumber.

unsigned getTargetFlags() const

MachineOperandType getType() const

getType - Returns the MachineOperandType for this operand.

const char * getSymbolName() const

void setIsUndef(bool Val=true)

bool isEarlyClobber() const

getReg - Returns the register number.

Intrinsic::ID getIntrinsicID() const

bool isInternalRead() const

void setTargetFlags(unsigned F)

bool isIdenticalTo(const MachineOperand &Other) const

Returns true if this operand is identical to the specified operand except for liveness related flags ...

const uint32_t * getRegMask() const

getRegMask - Returns a bit mask of registers preserved by this RegMask operand.

void setIsDef(bool Val=true)

Change a def to a use, or a use to a def.

void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const

Print the MachineOperand to os.

const ConstantFP * getFPImm() const

static void printSymbol(raw_ostream &OS, MCSymbol &Sym)

Print a MCSymbol as an operand.

unsigned getPredicate() const

MCSymbol * getMCSymbol() const

@ MO_CFIIndex

MCCFIInstruction index.

@ MO_Immediate

Immediate operand.

@ MO_ConstantPoolIndex

Address of indexed Constant in Constant Pool.

@ MO_MCSymbol

MCSymbol reference (for debug/eh info)

@ MO_Predicate

Generic predicate for ISel.

@ MO_GlobalAddress

Address of a global value.

@ MO_RegisterMask

Mask of preserved registers.

@ MO_ShuffleMask

Other IR Constant for ISel (shuffle masks)

@ MO_CImmediate

Immediate >64bit operand.

@ MO_BlockAddress

Address of a basic block.

@ MO_DbgInstrRef

Integer indices referring to an instruction+operand.

@ MO_MachineBasicBlock

MachineBasicBlock reference.

@ MO_FrameIndex

Abstract Stack Frame Index.

@ MO_Register

@ MO_ExternalSymbol

Name of external global symbol.

@ MO_IntrinsicID

Intrinsic ID for ISel.

@ MO_JumpTableIndex

Address of indexed Jump Table for switch.

@ MO_TargetIndex

Target-dependent index+offset operand.

@ MO_Metadata

Metadata reference (for debug info)

@ MO_FPImmediate

Floating-point immediate operand.

@ MO_RegisterLiveOut

Mask of live-out registers.

int64_t getOffset() const

Return the offset from the symbol in this operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

void removeRegOperandFromUseList(MachineOperand *MO)

Remove MO from its use-def list.

void addRegOperandToUseList(MachineOperand *MO)

Add MO to the linked list of operands for its register.

Manage lifetime of a slot tracker for printing IR.

int getLocalSlot(const Value *V)

Return the slot number of the specified local value.

const Function * getCurrentFunction() const

void incorporateFunction(const Function &F)

Incorporate the given function.

A Module instance is used to store all the information related to an LLVM module.

bool isNull() const

Test if the pointer held in the union is null, regardless of which type it is.

const PseudoSourceValue * getJumpTable()

Return a pseudo source value referencing a jump table.

const PseudoSourceValue * getFixedStack(int FI)

Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.

const PseudoSourceValue * getGOT()

Return a pseudo source value referencing the global offset table (or something the like).

const PseudoSourceValue * getStack()

Return a pseudo source value referencing the area below the stack frame of a function,...

const PseudoSourceValue * getConstantPool()

Return a pseudo source value referencing the constant pool.

Special value supplied for machine level alias analysis.

@ ExternalSymbolCallEntry

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

constexpr size_t size() const

size - Get the string size.

TargetInstrInfo - Interface to description of machine instruction set.

TargetIntrinsicInfo - Interface to description of machine instruction set.

virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0

Return the name of a target intrinsic, e.g.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

LLVM Value Representation.

void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const

Print the name of this Value out to the specified raw_ostream.

StringRef getName() const

Return a constant reference to the value's name.

An opaque object representing a hash code.

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

StringRef getBaseName(ID id)

Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....

@ System

Synchronized with respect to all concurrently executing threads.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

hash_code hash_value(const FixedPointSemantics &Val)

bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)

Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.

Printable printJumpTableEntryReference(unsigned Idx)

Prints a jump table entry reference.

const char * toIRString(AtomicOrdering ao)

String used by LLVM IR to represent atomic ordering.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)

Create Printable object to print register classes or register banks on a raw_ostream.

format_object< Ts... > format(const char *Fmt, const Ts &... Vals)

These are helper functions used to produce formatted output.

AtomicOrdering

Atomic ordering for LLVM's memory model.

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

Align commonAlignment(Align A, uint64_t Offset)

Returns the alignment that satisfies both alignments.

hash_code hash_combine(const Ts &...args)

Combine values into a single hash_code.

stable_hash stable_hash_combine(ArrayRef< stable_hash > Buffer)

void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)

Print out a name of an LLVM value without any prefixes.

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

MDNode * Scope

The tag for alias scope specification (used with noalias).

MDNode * TBAA

The tag for type-based alias analysis.

MDNode * NoAlias

The tag specifying the noalias scope.

This struct is a compact representation of a valid (non-zero power of two) alignment.

uint64_t value() const

This is a hole in the type system and should not be abused.

This class contains a discriminated union of information about pointers in memory operands,...

static MachinePointerInfo getJumpTable(MachineFunction &MF)

Return a MachinePointerInfo record that refers to a jump table entry.

bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const

Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.

unsigned getAddrSpace() const

Return the LLVM IR address space number that this pointer points into.

static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)

Stack pointer relative access.

int64_t Offset

Offset - This is an offset from the base Value*.

PointerUnion< const Value *, const PseudoSourceValue * > V

This is the IR pointer value for the access, or it is null if unknown.

static MachinePointerInfo getConstantPool(MachineFunction &MF)

Return a MachinePointerInfo record that refers to the constant pool.

static MachinePointerInfo getUnknownStack(MachineFunction &MF)

Stack memory without other information.

static MachinePointerInfo getGOT(MachineFunction &MF)

Return a MachinePointerInfo record that refers to a GOT entry.

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.