MachineOperand.h Source File (original) (raw)

13#ifndef LLVM_CODEGEN_MACHINEOPERAND_H

14#define LLVM_CODEGEN_MACHINEOPERAND_H

19#include

21namespace llvm {

23class LLT;

27class ConstantInt;

28class GlobalValue;

29class MachineBasicBlock;

30class MachineInstr;

31class MachineRegisterInfo;

32class MCCFIInstruction;

33class MDNode;

34class ModuleSlotTracker;

35class TargetIntrinsicInfo;

36class TargetRegisterInfo;

37class hash_code;

38class raw_ostream;

49public:

75private:

78 unsigned OpKind : 8;

84 unsigned SubReg_TargetFlags : 12;

89 unsigned TiedTo : 4;

94 unsigned IsDef : 1;

99 unsigned IsImp : 1;

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110 unsigned IsDeadOrKill : 1;

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113 unsigned IsRenamable : 1;

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132 unsigned IsUndef : 1;

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143 unsigned IsInternalRead : 1;

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148 unsigned IsEarlyClobber : 1;

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152 unsigned IsDebug : 1;

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156

157

158 union {

159 unsigned RegNo;

160 unsigned OffsetLo;

161 } SmallContents;

162

163

164

166

167

168 union ContentsUnion {

169 ContentsUnion() {}

170 MachineBasicBlock *MBB;

171 const ConstantFP *CFP;

172 const ConstantInt *CI;

173 int64_t ImmVal;

174 const uint32_t *RegMask;

175 const MDNode *MD;

176 MCSymbol *Sym;

177 unsigned CFIIndex;

178 Intrinsic::ID IntrinsicID;

179 unsigned Pred;

180 ArrayRef ShuffleMask;

181

182 struct {

183

184 MachineOperand *Prev;

185 MachineOperand *Next;

187

188 struct {

189 unsigned InstrIdx;

190 unsigned OpIdx;

191 } InstrRef;

192

193

194

195 struct {

196 union {

197 int Index;

198 const char *SymbolName;

199 const GlobalValue *GV;

200 const BlockAddress *BA;

201 } Val;

202

203 int OffsetHi;

204 } OffsetedInfo;

205 } Contents;

206

208 : OpKind(K), SubReg_TargetFlags(0) {

209

210 static_assert(alignof(MachineOperand) <= alignof(int64_t),

211 "MachineOperand shouldn't be more than 8 byte aligned");

212 static_assert(sizeof(Contents) <= 2 * sizeof(void *),

213 "Contents should be at most two pointers");

214 static_assert(sizeof(MachineOperand) <=

216 3 * sizeof(void *)),

217 "MachineOperand too big. Should be Kind, SmallContents, "

218 "ParentMI, and Contents");

219 }

220

221public:

222

223

225

227 return isReg() ? 0 : SubReg_TargetFlags;

228 }

230 assert( isReg () && "Register operands can't have target flags");

231 SubReg_TargetFlags = F;

232 assert(SubReg_TargetFlags == F && "Target flags out of range");

233 }

235 assert( isReg () && "Register operands can't have target flags");

236 SubReg_TargetFlags |= F;

237 assert((SubReg_TargetFlags & F) && "Target flags out of range");

238 }

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311 std::optional OpIdx, bool PrintDef, bool IsStandalone,

312 bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,

315

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321

322 void dump() const;

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370 assert(isReg() && "This is not a register operand!");

371 return Register(SmallContents.RegNo);

372 }

373

375 assert(isReg() && "Wrong MachineOperand accessor");

376 return SubReg_TargetFlags;

377 }

378

380 assert(isReg() && "Wrong MachineOperand accessor");

381 return !IsDef;

382 }

383

385 assert(isReg() && "Wrong MachineOperand accessor");

386 return IsDef;

387 }

388

390 assert(isReg() && "Wrong MachineOperand accessor");

391 return IsImp;

392 }

393

395 assert(isReg() && "Wrong MachineOperand accessor");

396 return IsDeadOrKill & IsDef;

397 }

398

400 assert(isReg() && "Wrong MachineOperand accessor");

401 return IsDeadOrKill & !IsDef;

402 }

403

405 assert(isReg() && "Wrong MachineOperand accessor");

406 return IsUndef;

407 }

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441 assert(isReg() && "Wrong MachineOperand accessor");

442 return IsInternalRead;

443 }

444

446 assert(isReg() && "Wrong MachineOperand accessor");

447 return IsEarlyClobber;

448 }

449

451 assert(isReg() && "Wrong MachineOperand accessor");

452 return TiedTo;

453 }

454

456 assert(isReg() && "Wrong MachineOperand accessor");

457 return IsDebug;

458 }

459

460

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465

466

468 assert(isReg() && "Wrong MachineOperand accessor");

470 }

471

472

473

476 return true;

477

478

480 }

481

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489

491 assert(isReg() && "Wrong MachineOperand mutator");

492 SubReg_TargetFlags = subReg;

493 assert(SubReg_TargetFlags == subReg && "SubReg out of range");

494 }

495

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512 void setIsDef(bool Val = true);

513

515 assert(isReg() && "Wrong MachineOperand mutator");

516 IsImp = Val;

517 }

518

520 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");

521 assert((!Val || isDebug ()) && "Marking a debug operation as kill");

522 IsDeadOrKill = Val;

523 }

524

526 assert(isReg() && IsDef && "Wrong MachineOperand mutator");

527 IsDeadOrKill = Val;

528 }

529

531 assert(isReg() && "Wrong MachineOperand mutator");

532 IsUndef = Val;

533 }

534

536

538 assert(isReg() && "Wrong MachineOperand mutator");

539 IsInternalRead = Val;

540 }

541

543 assert(isReg() && IsDef && "Wrong MachineOperand mutator");

544 IsEarlyClobber = Val;

545 }

546

548 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");

549 IsDebug = Val;

550 }

551

552

553

554

555

557 assert(isImm() && "Wrong MachineOperand accessor");

558 return Contents.ImmVal;

559 }

560

562 assert(isCImm() && "Wrong MachineOperand accessor");

563 return Contents.CI;

564 }

565

567 assert(isFPImm() && "Wrong MachineOperand accessor");

568 return Contents.CFP;

569 }

570

572 assert(isMBB() && "Wrong MachineOperand accessor");

573 return Contents.MBB;

574 }

575

578 "Wrong MachineOperand accessor");

579 return Contents.OffsetedInfo.Val.Index;

580 }

581

583 assert(isGlobal() && "Wrong MachineOperand accessor");

584 return Contents.OffsetedInfo.Val.GV;

585 }

586

589 return Contents.OffsetedInfo.Val.BA;

590 }

591

594 return Contents.Sym;

595 }

596

599 return Contents.InstrRef.InstrIdx;

600 }

601

604 return Contents.InstrRef.OpIdx;

605 }

606

609 return Contents.CFIIndex;

610 }

611

614 return Contents.IntrinsicID;

615 }

616

619 return Contents.Pred;

620 }

621

624 return Contents.ShuffleMask;

625 }

626

627

628

632 "Wrong MachineOperand accessor");

633 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |

634 SmallContents.OffsetLo;

635 }

636

638 assert(isSymbol() && "Wrong MachineOperand accessor");

639 return Contents.OffsetedInfo.Val.SymbolName;

640 }

641

642

643

644

645

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649 "Not a physical register");

650 return !(RegMask[PhysReg.id() / 32] & (1u << PhysReg.id() % 32));

651 }

652

653

656 }

657

658

659

662 return Contents.RegMask;

663 }

664

665

667 return (NumRegs + 31) / 32;

668 }

669

670

673 return Contents.RegMask;

674 }

675

678 return Contents.MD;

679 }

680

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684

686 assert(isImm() && "Wrong MachineOperand mutator");

687 Contents.ImmVal = immVal;

688 }

689

691 assert(isCImm() && "Wrong MachineOperand mutator");

692 Contents.CI = CI;

693 }

694

696 assert(isFPImm() && "Wrong MachineOperand mutator");

697 Contents.CFP = CFP;

698 }

699

703 "Wrong MachineOperand mutator");

705 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);

706 }

707

710 "Wrong MachineOperand mutator");

711 Contents.OffsetedInfo.Val.Index = Idx;

712 }

713

716 Contents.MD = MD;

717 }

718

721 Contents.InstrRef.InstrIdx = InstrIdx;

722 }

725 Contents.InstrRef.OpIdx = OpIdx;

726 }

727

729 assert(isMBB() && "Wrong MachineOperand mutator");

730 Contents.MBB = MBB;

731 }

732

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739 Contents.RegMask = RegMaskPtr;

740 }

741

744 Contents.IntrinsicID = IID;

745 }

746

749 Contents.Pred = Predicate;

750 }

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772 void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);

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780 void ChangeToES(const char *SymName, unsigned TargetFlags = 0);

781

782

784 unsigned TargetFlags = 0);

785

786

788 unsigned TargetFlags = 0);

789

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798 unsigned TargetFlags = 0);

799

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802 unsigned TargetFlags = 0);

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819

822 Op.setImm(Val);

823 return Op;

824 }

825

828 Op.Contents.CI = CI;

829 return Op;

830 }

831

834 Op.Contents.CFP = CFP;

835 return Op;

836 }

837

849 Op.IsImp = isImp;

855 Op.TiedTo = 0;

857 Op.SmallContents.RegNo = Reg;

858 Op.Contents.Reg.Prev = nullptr;

859 Op.Contents.Reg.Next = nullptr;

861 return Op;

862 }

864 unsigned TargetFlags = 0) {

867 Op.setTargetFlags(TargetFlags);

868 return Op;

869 }

872 Op.setIndex(Idx);

873 return Op;

874 }

876 unsigned TargetFlags = 0) {

878 Op.setIndex(Idx);

880 Op.setTargetFlags(TargetFlags);

881 return Op;

882 }

884 unsigned TargetFlags = 0) {

886 Op.setIndex(Idx);

888 Op.setTargetFlags(TargetFlags);

889 return Op;

890 }

893 Op.setIndex(Idx);

894 Op.setTargetFlags(TargetFlags);

895 return Op;

896 }

898 unsigned TargetFlags = 0) {

900 Op.Contents.OffsetedInfo.Val.GV = GV;

902 Op.setTargetFlags(TargetFlags);

903 return Op;

904 }

906 unsigned TargetFlags = 0) {

908 Op.Contents.OffsetedInfo.Val.SymbolName = SymName;

909 Op.setOffset(0);

910 Op.setTargetFlags(TargetFlags);

911 return Op;

912 }

914 unsigned TargetFlags = 0) {

916 Op.Contents.OffsetedInfo.Val.BA = BA;

918 Op.setTargetFlags(TargetFlags);

919 return Op;

920 }

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934 assert(Mask && "Missing register mask");

936 Op.Contents.RegMask = Mask;

937 return Op;

938 }

940 assert(Mask && "Missing live-out register mask");

942 Op.Contents.RegMask = Mask;

943 return Op;

944 }

947 Op.Contents.MD = Meta;

948 return Op;

949 }

950

952 unsigned TargetFlags = 0) {

954 Op.Contents.Sym = Sym;

955 Op.setOffset(0);

956 Op.setTargetFlags(TargetFlags);

957 return Op;

958 }

959

962 Op.Contents.InstrRef.InstrIdx = InstrIdx;

963 Op.Contents.InstrRef.OpIdx = OpIdx;

964 return Op;

965 }

966

969 Op.Contents.CFIIndex = CFIIndex;

970 return Op;

971 }

972

975 Op.Contents.IntrinsicID = ID;

976 return Op;

977 }

978

981 Op.Contents.Pred = Pred;

982 return Op;

983 }

984

987 Op.Contents.ShuffleMask = Mask;

988 return Op;

989 }

990

993

994private:

995

996

997 void removeRegFromUses();

998

999

1000 enum : unsigned char {

1002 MO_Tombstone,

1003 };

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1014 bool isOnRegUseList() const {

1015 assert(isReg() && "Can only add reg operand to use lists");

1016 return Contents.Reg.Prev != nullptr;

1017 }

1018};

1019

1023 MachineOperand::MO_Empty));

1024 }

1027 MachineOperand::MO_Tombstone));

1028 }

1031 }

1034 MachineOperand::MO_Empty) ||

1036 MachineOperand::MO_Tombstone))

1037 return LHS.getType() == RHS.getType();

1038 return LHS.isIdenticalTo(RHS);

1039 }

1040};

1041

1044 return OS;

1045}

1046

1047

1048

1049hash_code hash_value(const MachineOperand &MO);

1050}

1051

1052#endif

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

This file defines DenseMapInfo traits for DenseMap.

unsigned const TargetRegisterInfo * TRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

The address of a basic block.

ConstantFP - Floating Point Values [float, double].

This is the shared class of boolean and integer constants.

This class represents an Operation in the Expression.

Wrapper class representing physical registers. Should be passed by value.

constexpr bool isValid() const

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

constexpr unsigned id() const

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

void setSubReg(unsigned subReg)

unsigned getSubReg() const

void setIsUse(bool Val=true)

static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)

unsigned getInstrRefOpIndex() const

void setInstrRefInstrIndex(unsigned InstrIdx)

unsigned getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

const GlobalValue * getGlobal() const

void setImplicit(bool Val=true)

void setIsInternalRead(bool Val=true)

void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)

Replace this operand with a frame index.

const uint32_t * getRegLiveOut() const

getRegLiveOut - Returns a bit mask of live-out registers.

void setInstrRefOpIndex(unsigned OpIdx)

static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)

const ConstantInt * getCImm() const

const char * getTargetIndexName() const

getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...

static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)

Print a stack object reference.

static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)

Print a subreg index operand.

static MachineOperand CreateFPImm(const ConstantFP *CFP)

void setImm(int64_t immVal)

bool isCImm() const

isCImm - Test if this is a MO_CImmediate operand.

void setRegMask(const uint32_t *RegMaskPtr)

Sets value of register mask operand referencing Mask.

unsigned getInstrRefInstrIndex() const

static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)

Print operand target flags.

bool readsReg() const

readsReg - Returns true if this operand reads the previous value of its register.

static MachineOperand CreateCFIIndex(unsigned CFIIndex)

void setFPImm(const ConstantFP *CFP)

void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)

ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.

bool isIntrinsicID() const

void setIsRenamable(bool Val=true)

static MachineOperand CreateRegMask(const uint32_t *Mask)

CreateRegMask - Creates a register mask operand referencing Mask.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isRegMask() const

isRegMask - Tests if this is a MO_RegisterMask operand.

const MDNode * getMetadata() const

MachineBasicBlock * getMBB() const

bool isCPI() const

isCPI - Tests if this is a MO_ConstantPoolIndex operand.

friend hash_code hash_value(const MachineOperand &MO)

MachineOperand hash_value overload.

static MachineOperand CreateCImm(const ConstantInt *CI)

void setIsDead(bool Val=true)

ArrayRef< int > getShuffleMask() const

void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)

ChangeToMCSymbol - Replace this operand with a new MC symbol operand.

void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)

Replace this operand with a target index.

void setReg(Register Reg)

Change the register this operand corresponds to.

void setMetadata(const MDNode *MD)

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

bool isValidExcessOperand() const

Return true if this operand can validly be appended to an arbitrary operand list.

void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

bool isMetadata() const

isMetadata - Tests if this is a MO_Metadata operand.

bool clobbersPhysReg(MCRegister PhysReg) const

clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.

bool isSymbol() const

isSymbol - Tests if this is a MO_ExternalSymbol operand.

void ChangeToES(const char *SymName, unsigned TargetFlags=0)

ChangeToES - Replace this operand with a new external symbol operand.

void clearParent()

clearParent - Reset the parent pointer.

bool isShuffleMask() const

void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)

ChangeToGA - Replace this operand with a new global address operand.

unsigned getCFIIndex() const

void setIsKill(bool Val=true)

bool isRenamable() const

isRenamable - Returns true if this register may be renamed, i.e.

void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)

ChangeToBA - Replace this operand with a new block address operand.

bool isJTI() const

isJTI - Tests if this is a MO_JumpTableIndex operand.

static MachineOperand CreateMetadata(const MDNode *Meta)

static void printOperandOffset(raw_ostream &OS, int64_t Offset)

Print the offset with explicit +/- signs.

void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)

Replace this operand with an Instruction Reference.

void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)

ChangeToRegister - Replace this operand with a new register operand of the specified value.

const BlockAddress * getBlockAddress() const

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...

static MachineOperand CreatePredicate(unsigned Pred)

void setMBB(MachineBasicBlock *MBB)

bool isRegLiveOut() const

isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.

void setIsEarlyClobber(bool Val=true)

static unsigned getRegMaskSize(unsigned NumRegs)

Returns number of elements needed for a regmask array.

void setOffset(int64_t Offset)

void setCImm(const ConstantInt *CI)

static void printIRSlotNumber(raw_ostream &OS, int Slot)

Print an IRSlotNumber.

unsigned getTargetFlags() const

static MachineOperand CreateImm(int64_t Val)

bool isGlobal() const

isGlobal - Tests if this is a MO_GlobalAddress operand.

void setPredicate(unsigned Predicate)

static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)

MachineOperandType getType() const

getType - Returns the MachineOperandType for this operand.

static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)

const char * getSymbolName() const

static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)

void setIsUndef(bool Val=true)

void setIsDebug(bool Val=true)

bool isEarlyClobber() const

bool isBlockAddress() const

isBlockAddress - Tests if this is a MO_BlockAddress operand.

getReg - Returns the register number.

bool isTargetIndex() const

isTargetIndex - Tests if this is a MO_TargetIndex operand.

static MachineOperand CreateRegLiveOut(const uint32_t *Mask)

static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)

void setIntrinsicID(Intrinsic::ID IID)

void addTargetFlag(unsigned F)

bool isDbgInstrRef() const

Intrinsic::ID getIntrinsicID() const

bool isInternalRead() const

static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)

void setTargetFlags(unsigned F)

bool isFI() const

isFI - Tests if this is a MO_FrameIndex operand.

bool isIdenticalTo(const MachineOperand &Other) const

Returns true if this operand is identical to the specified operand except for liveness related flags ...

static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

const uint32_t * getRegMask() const

getRegMask - Returns a bit mask of registers preserved by this RegMask operand.

static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)

void setIsDef(bool Val=true)

Change a def to a use, or a use to a def.

void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const

Print the MachineOperand to os.

const ConstantFP * getFPImm() const

static void printSymbol(raw_ostream &OS, MCSymbol &Sym)

Print a MCSymbol as an operand.

const MachineInstr * getParent() const

unsigned getPredicate() const

MCSymbol * getMCSymbol() const

@ MO_CFIIndex

MCCFIInstruction index.

@ MO_Immediate

Immediate operand.

@ MO_ConstantPoolIndex

Address of indexed Constant in Constant Pool.

@ MO_MCSymbol

MCSymbol reference (for debug/eh info)

@ MO_Predicate

Generic predicate for ISel.

@ MO_GlobalAddress

Address of a global value.

@ MO_RegisterMask

Mask of preserved registers.

@ MO_ShuffleMask

Other IR Constant for ISel (shuffle masks)

@ MO_CImmediate

Immediate >64bit operand.

@ MO_BlockAddress

Address of a basic block.

@ MO_DbgInstrRef

Integer indices referring to an instruction+operand.

@ MO_MachineBasicBlock

MachineBasicBlock reference.

@ MO_FrameIndex

Abstract Stack Frame Index.

@ MO_Register

@ MO_ExternalSymbol

Name of external global symbol.

@ MO_IntrinsicID

Intrinsic ID for ISel.

@ MO_JumpTableIndex

Address of indexed Jump Table for switch.

@ MO_TargetIndex

Target-dependent index+offset operand.

@ MO_Metadata

Metadata reference (for debug info)

@ MO_FPImmediate

Floating-point immediate operand.

@ MO_RegisterLiveOut

Mask of live-out registers.

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)

static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)

int64_t getOffset() const

Return the offset from the symbol in this operand.

static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)

bool isFPImm() const

isFPImm - Tests if this is a MO_FPImmediate operand.

static MachineOperand CreateFI(int Idx)

bool isMBB() const

isMBB - Tests if this is a MO_MachineBasicBlock operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Manage lifetime of a slot tracker for printing IR.

Wrapper class representing virtual and physical registers.

StringRef - Represent a constant reference to a string, i.e.

TargetIntrinsicInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

An opaque object representing a hash code.

This class implements an extremely fast bulk output stream that can only output to a stream.

constexpr char SymbolName[]

Key for Kernel::Metadata::mSymbolName.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Reg

All possible values of the reg field in the ModR/M byte.

This is an optimization pass for GlobalISel generic memory operations.

hash_code hash_value(const FixedPointSemantics &Val)

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

DWARFExpression::Operation Op

raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)

static unsigned getHashValue(const MachineOperand &MO)

static MachineOperand getTombstoneKey()

static MachineOperand getEmptyKey()

static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS)

An information struct used to provide DenseMap with the various necessary components for a given valu...