LLVM: lib/CodeGen/MachineSSAContext.cpp Source File (original) (raw)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

22

23using namespace llvm;

24

25template <>

29 for (auto &op : instr.all_defs())

31 }

32}

33

34template <>

37 for (auto &T : block.terminators())

39}

40

41template <>

45 for (auto &T : block.terminators())

47}

48

49

50template <>

52 if (!value)

53 return nullptr;

54 return F->getRegInfo().getVRegDef(value)->getParent();

55}

56

58 return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||

59 MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;

60}

61

62

63template <>

65 if (Phi.isPHI())

66 return false;

67

68

69 if (Phi.getOpcode() == TargetOpcode::PHI)

70 return Phi.isConstantValuePHI().isValid();

71

72

73 const MachineRegisterInfo &MRI = Phi.getMF()->getRegInfo();

76 for (unsigned i = 1, e = Phi.getNumOperands(); i < e; i += 2) {

77 Register Incoming = Phi.getOperand(i).getReg();

78 if (Incoming != This && isUndef(*MRI.getVRegDef(Incoming))) {

79 if (ConstantValue && ConstantValue != Incoming)

80 return false;

81 ConstantValue = Incoming;

82 }

83 }

84 return true;

85}

86

87template <>

90 return GI->getIntrinsicID();

92}

93

94template <>

97 return Printable([](raw_ostream &Out) { Out << ""; });

98 return Printable([Block](raw_ostream &Out) { Block->printName(Out); });

99}

100

102 return Printable([I](raw_ostream &Out) { I->print(Out); });

103}

104

106 auto *MRI = &F->getRegInfo();

107 return Printable([MRI, Value](raw_ostream &Out) {

109

111

112 if (auto *Instr = MRI->getUniqueVRegDef(Value)) {

113 Out << ": ";

114 Instr->print(Out);

115 }

116 }

117 });

118}

119

120template <>

122 return Printable([BB](raw_ostream &Out) { BB->printAsOperand(Out); });

123}

unsigned const MachineRegisterInfo * MRI

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

static bool isUndef(const MachineInstr &MI)

Definition MachineSSAContext.cpp:57

This file declares a specialization of the GenericSSAContext template class for Machine IR.

Promote Memory to Register

unify loop Fixup each natural loop to have a single exit block

static void appendBlockDefs(SmallVectorImpl< ValueRefT > &defs, BlockT &block)

static bool isConstantOrUndefValuePhi(const InstructionT &Instr)

static void appendBlockTerms(SmallVectorImpl< InstructionT * > &terms, BlockT &block)

static Intrinsic::ID getIntrinsicID(const InstructionT &I)

Printable print(const BlockT *block) const

const BlockT * getDefBlock(ConstValueRefT value) const

Printable printAsOperand(const BlockT *BB) const

LLVM_ABI void printAsOperand(raw_ostream &OS, bool PrintType=true) const

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

Representation of each machine instruction.

Simple wrapper around std::function<void(raw_ostream&)>.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

LLVM Value Representation.

NodeAddr< InstrNode * > Instr

NodeAddr< PhiNode * > Phi

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.