LLVM: lib/MCA/Stages/MicroOpQueueStage.cpp Source File (original) (raw)

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16namespace llvm {

17namespace mca {

18

19#define DEBUG_TYPE "llvm-mca"

20

21Error MicroOpQueueStage::moveInstructions() {

22 InstRef IR = Buffer[CurrentInstructionSlotIdx];

25 return Val;

26

27 Buffer[CurrentInstructionSlotIdx].invalidate();

28 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);

29 CurrentInstructionSlotIdx += NormalizedOpcodes;

30 CurrentInstructionSlotIdx %= Buffer.size();

31 AvailableEntries += NormalizedOpcodes;

32 IR = Buffer[CurrentInstructionSlotIdx];

33 }

34

36}

37

38MicroOpQueueStage::MicroOpQueueStage(unsigned Size, unsigned IPC,

39 bool ZeroLatencyStage)

40 : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0), MaxIPC(IPC),

41 CurrentIPC(0), IsZeroLatencyStage(ZeroLatencyStage) {

42 Buffer.resize(Size ? Size : 1);

43 AvailableEntries = Buffer.size();

44}

45

47 Buffer[NextAvailableSlotIdx] = IR;

48 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR);

49 NextAvailableSlotIdx += NormalizedOpcodes;

50 NextAvailableSlotIdx %= Buffer.size();

51 AvailableEntries -= NormalizedOpcodes;

52 ++CurrentIPC;

54}

55

57 CurrentIPC = 0;

58 if (!IsZeroLatencyStage)

59 return moveInstructions();

61}

62

64 if (IsZeroLatencyStage)

65 return moveInstructions();

67}

68

69}

70}

Legalize the Machine IR a function s Machine IR

This file defines a stage that implements a queue of micro opcodes.

Subclass of Error for the sole purpose of identifying the success path in the type system.

Lightweight error class with error context and mandatory checking.

An InstRef contains both a SourceMgr index and Instruction pair.

Error cycleEnd() override

Called once at the end of each cycle.

Definition MicroOpQueueStage.cpp:63

Error execute(InstRef &IR) override

The primary action that this stage performs on instruction IR.

Definition MicroOpQueueStage.cpp:46

Error cycleStart() override

Called once at the start of each cycle.

Definition MicroOpQueueStage.cpp:56

Error moveToTheNextStage(InstRef &IR)

Called when an instruction is ready to move the next pipeline stage.

bool checkNextStage(const InstRef &IR) const

This is an optimization pass for GlobalISel generic memory operations.