LLVM: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Source File (original) (raw)

36

37 unsigned Kind = Fixup.getKind();

38

39

40 switch (Kind) {

41 default:

42 return 0;

61 break;

64 Ctx.reportError(Fixup.getLoc(),

65 "fixup value out of range [-32768, 65535]");

66 break;

76 break;

78

79

81

83 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");

84 return 0;

85 }

86 break;

89

91

93 Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup");

94 return 0;

95 }

96 break;

98

99

100

102 break;

110

111 Value = ((Value + 0x8000) >> 16) & 0xffff;

112 break;

115

116 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;

117 break;

120

121 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;

122 break;

125 break;

128

130

132 Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup");

133 return 0;

134 }

135 break;

138

140

142 Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup");

143 return 0;

144 }

145 break;

148

150

152 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");

153 return 0;

154 }

155 break;

157

159

161 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");

162 return 0;

163 }

164 break;

166

167 if ((Value & 7)) {

168 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");

169 }

170

172

174 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");

175 return 0;

176 }

177 break;

179

181

183 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");

184 return 0;

185 }

186 break;

188

190

192 Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup");

193 return 0;

194 }

195 break;

197

199

201 Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup");

202 return 0;

203 }

204 break;

206

208

210 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");

211 return 0;

212 }

213 break;

214 }

215

217}

236 assert(i <= 3 && "Index out of range!");

237

238 return (1 - i / 2) * 2 + i % 2;

239}

244 default:

245 return false;

246

247

278 return true;

279 }

280}

289 IsResolved = false;

294

296 return;

297

298

299

301

302 unsigned FullSize;

303

304 switch ((unsigned)Kind) {

308 FullSize = 2;

309 break;

312 FullSize = 8;

313 break;

315 default:

316 FullSize = 4;

317 break;

318 }

319

320

322

324

325 for (unsigned i = 0; i != NumBytes; ++i) {

328 : (FullSize - 1 - i);

330 }

331

334 CurVal |= Value & Mask;

335

336

337 for (unsigned i = 0; i != NumBytes; ++i) {

340 : (FullSize - 1 - i);

341 Data[Idx] = (uint8_t)((CurVal >> (i * 8)) & 0xff);

342 }

343}

347 .Case("BFD_RELOC_NONE", ELF::R_MIPS_NONE)

348 .Case("BFD_RELOC_16", ELF::R_MIPS_16)

349 .Case("BFD_RELOC_32", ELF::R_MIPS_32)

350 .Case("BFD_RELOC_64", ELF::R_MIPS_64)

352 if (Type != -1u)

354

356 .Case("R_MIPS_NONE", FK_NONE)

380 .Case("R_MICROMIPS_TLS_DTPREL_HI16",

382 .Case("R_MICROMIPS_TLS_DTPREL_LO16",

391}

395

396

397

398

399

400 { "fixup_Mips_16", 0, 16, 0 },

401 { "fixup_Mips_32", 0, 32, 0 },

402 { "fixup_Mips_REL32", 0, 32, 0 },

403 { "fixup_Mips_GPREL32", 0, 32, 0 },

404 { "fixup_Mips_DTPREL32", 0, 32, 0 },

405 { "fixup_Mips_DTPREL64", 0, 64, 0 },

406 { "fixup_Mips_TPREL32", 0, 32, 0 },

407 { "fixup_Mips_TPREL64", 0, 64, 0 },

408 { "fixup_Mips_26", 0, 26, 0 },

409 { "fixup_Mips_HI16", 0, 16, 0 },

410 { "fixup_Mips_LO16", 0, 16, 0 },

411 { "fixup_Mips_AnyImm16", 0, 16, 0 },

412 { "fixup_Mips_GPREL16", 0, 16, 0 },

413 { "fixup_Mips_LITERAL", 0, 16, 0 },

414 { "fixup_Mips_GOT", 0, 16, 0 },

415 { "fixup_Mips_PC16", 0, 16, 0 },

416 { "fixup_Mips_CALL16", 0, 16, 0 },

417 { "fixup_Mips_SHIFT5", 6, 5, 0 },

418 { "fixup_Mips_SHIFT6", 6, 5, 0 },

419 { "fixup_Mips_64", 0, 64, 0 },

420 { "fixup_Mips_TLSGD", 0, 16, 0 },

421 { "fixup_Mips_GOTTPREL", 0, 16, 0 },

422 { "fixup_Mips_TPREL_HI", 0, 16, 0 },

423 { "fixup_Mips_TPREL_LO", 0, 16, 0 },

424 { "fixup_Mips_TLSLDM", 0, 16, 0 },

425 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },

426 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },

427 { "fixup_Mips_Branch_PCRel", 0, 16, 0 },

428 { "fixup_Mips_GPOFF_HI", 0, 16, 0 },

429 { "fixup_MICROMIPS_GPOFF_HI",0, 16, 0 },

430 { "fixup_Mips_GPOFF_LO", 0, 16, 0 },

431 { "fixup_MICROMIPS_GPOFF_LO",0, 16, 0 },

432 { "fixup_Mips_GOT_PAGE", 0, 16, 0 },

433 { "fixup_Mips_GOT_OFST", 0, 16, 0 },

434 { "fixup_Mips_GOT_DISP", 0, 16, 0 },

435 { "fixup_Mips_HIGHER", 0, 16, 0 },

436 { "fixup_MICROMIPS_HIGHER", 0, 16, 0 },

437 { "fixup_Mips_HIGHEST", 0, 16, 0 },

438 { "fixup_MICROMIPS_HIGHEST", 0, 16, 0 },

439 { "fixup_Mips_GOT_HI16", 0, 16, 0 },

440 { "fixup_Mips_GOT_LO16", 0, 16, 0 },

441 { "fixup_Mips_CALL_HI16", 0, 16, 0 },

442 { "fixup_Mips_CALL_LO16", 0, 16, 0 },

443 { "fixup_Mips_PC18_S3", 0, 18, 0 },

444 { "fixup_MIPS_PC19_S2", 0, 19, 0 },

445 { "fixup_MIPS_PC21_S2", 0, 21, 0 },

446 { "fixup_MIPS_PC26_S2", 0, 26, 0 },

447 { "fixup_MIPS_PCHI16", 0, 16, 0 },

448 { "fixup_MIPS_PCLO16", 0, 16, 0 },

449 { "fixup_MICROMIPS_26_S1", 0, 26, 0 },

450 { "fixup_MICROMIPS_HI16", 0, 16, 0 },

451 { "fixup_MICROMIPS_LO16", 0, 16, 0 },

452 { "fixup_MICROMIPS_GOT16", 0, 16, 0 },

453 { "fixup_MICROMIPS_PC7_S1", 0, 7, 0 },

454 { "fixup_MICROMIPS_PC10_S1", 0, 10, 0 },

455 { "fixup_MICROMIPS_PC16_S1", 0, 16, 0 },

456 { "fixup_MICROMIPS_PC26_S1", 0, 26, 0 },

457 { "fixup_MICROMIPS_PC19_S2", 0, 19, 0 },

458 { "fixup_MICROMIPS_PC18_S3", 0, 18, 0 },

459 { "fixup_MICROMIPS_PC21_S1", 0, 21, 0 },

460 { "fixup_MICROMIPS_CALL16", 0, 16, 0 },

461 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },

462 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },

463 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },

464 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },

465 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },

466 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },

467 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },

468 { "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 },

469 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },

470 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 },

471 { "fixup_Mips_SUB", 0, 64, 0 },

472 { "fixup_MICROMIPS_SUB", 0, 64, 0 },

473 { "fixup_Mips_JALR", 0, 32, 0 },

474 { "fixup_MICROMIPS_JALR", 0, 32, 0 },

475

476 };

478 "Not all MIPS little endian fixup kinds added!");

479

481

482

483

484

485

486 { "fixup_Mips_16", 16, 16, 0 },

487 { "fixup_Mips_32", 0, 32, 0 },

488 { "fixup_Mips_REL32", 0, 32, 0 },

489 { "fixup_Mips_GPREL32", 0, 32, 0 },

490 { "fixup_Mips_DTPREL32", 0, 32, 0 },

491 { "fixup_Mips_DTPREL64", 0, 64, 0 },

492 { "fixup_Mips_TPREL32", 0, 32, 0 },

493 { "fixup_Mips_TPREL64", 0, 64, 0 },

494 { "fixup_Mips_26", 6, 26, 0 },

495 { "fixup_Mips_HI16", 16, 16, 0 },

496 { "fixup_Mips_LO16", 16, 16, 0 },

497 { "fixup_Mips_AnyImm16", 16, 16, 0 },

498 { "fixup_Mips_GPREL16", 16, 16, 0 },

499 { "fixup_Mips_LITERAL", 16, 16, 0 },

500 { "fixup_Mips_GOT", 16, 16, 0 },

501 { "fixup_Mips_PC16", 16, 16, 0 },

502 { "fixup_Mips_CALL16", 16, 16, 0 },

503 { "fixup_Mips_SHIFT5", 21, 5, 0 },

504 { "fixup_Mips_SHIFT6", 21, 5, 0 },

505 { "fixup_Mips_64", 0, 64, 0 },

506 { "fixup_Mips_TLSGD", 16, 16, 0 },

507 { "fixup_Mips_GOTTPREL", 16, 16, 0 },

508 { "fixup_Mips_TPREL_HI", 16, 16, 0 },

509 { "fixup_Mips_TPREL_LO", 16, 16, 0 },

510 { "fixup_Mips_TLSLDM", 16, 16, 0 },

511 { "fixup_Mips_DTPREL_HI", 16, 16, 0 },

512 { "fixup_Mips_DTPREL_LO", 16, 16, 0 },

513 { "fixup_Mips_Branch_PCRel",16, 16, 0 },

514 { "fixup_Mips_GPOFF_HI", 16, 16, 0 },

515 { "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 },

516 { "fixup_Mips_GPOFF_LO", 16, 16, 0 },

517 { "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 },

518 { "fixup_Mips_GOT_PAGE", 16, 16, 0 },

519 { "fixup_Mips_GOT_OFST", 16, 16, 0 },

520 { "fixup_Mips_GOT_DISP", 16, 16, 0 },

521 { "fixup_Mips_HIGHER", 16, 16, 0 },

522 { "fixup_MICROMIPS_HIGHER", 16, 16, 0 },

523 { "fixup_Mips_HIGHEST", 16, 16, 0 },

524 { "fixup_MICROMIPS_HIGHEST",16, 16, 0 },

525 { "fixup_Mips_GOT_HI16", 16, 16, 0 },

526 { "fixup_Mips_GOT_LO16", 16, 16, 0 },

527 { "fixup_Mips_CALL_HI16", 16, 16, 0 },

528 { "fixup_Mips_CALL_LO16", 16, 16, 0 },

529 { "fixup_Mips_PC18_S3", 14, 18, 0 },

530 { "fixup_MIPS_PC19_S2", 13, 19, 0 },

531 { "fixup_MIPS_PC21_S2", 11, 21, 0 },

532 { "fixup_MIPS_PC26_S2", 6, 26, 0 },

533 { "fixup_MIPS_PCHI16", 16, 16, 0 },

534 { "fixup_MIPS_PCLO16", 16, 16, 0 },

535 { "fixup_MICROMIPS_26_S1", 6, 26, 0 },

536 { "fixup_MICROMIPS_HI16", 16, 16, 0 },

537 { "fixup_MICROMIPS_LO16", 16, 16, 0 },

538 { "fixup_MICROMIPS_GOT16", 16, 16, 0 },

539 { "fixup_MICROMIPS_PC7_S1", 9, 7, 0 },

540 { "fixup_MICROMIPS_PC10_S1", 6, 10, 0 },

541 { "fixup_MICROMIPS_PC16_S1",16, 16, 0 },

542 { "fixup_MICROMIPS_PC26_S1", 6, 26, 0 },

543 { "fixup_MICROMIPS_PC19_S2",13, 19, 0 },

544 { "fixup_MICROMIPS_PC18_S3",14, 18, 0 },

545 { "fixup_MICROMIPS_PC21_S1",11, 21, 0 },

546 { "fixup_MICROMIPS_CALL16", 16, 16, 0 },

547 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },

548 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },

549 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },

550 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },

551 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },

552 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },

553 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },

554 { "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 },

555 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },

556 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 },

557 { "fixup_Mips_SUB", 0, 64, 0 },

558 { "fixup_MICROMIPS_SUB", 0, 64, 0 },

559 { "fixup_Mips_JALR", 0, 32, 0 },

560 { "fixup_MICROMIPS_JALR", 0, 32, 0 },

561

562 };

564 "Not all MIPS big endian fixup kinds added!");

565

567 return {};

570

572 "Invalid kind!");

573

577}

586

587

588

589

590

591

592

594 return true;

595}

619 return new WindowsMipsAsmBackend(T, MRI, STI);

620

624 ABI.IsN32());

625}