MipsISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H

15#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H

34#include

35#include

36#include

37#include

39namespace llvm {

59 bool isMicroMips;

61 public:

88 EVT VT) const override;

94 EVT VT) const override;

99 unsigned &NumIntermediates, MVT &RegisterVT) const override;

100

101

104 const Align ABIAlign = DL.getABITypeAlign(ArgTy);

106 return std::min(ABIAlign, Align(8));

107 return ABIAlign;

108 }

109

113

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122

123

125 EVT VT) const override;

126

128

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142

145 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;

146 }

147

148

149

152 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;

153 }

154

156

160

162

164

165 protected:

167

168

169

170

171

172 template

174 bool IsN32OrN64) const {

177 getTargetNode(N, Ty, DAG, GOTFlag));

183 getTargetNode(N, Ty, DAG, LoFlag));

185 }

186

187

188

189

190

191 template

193 unsigned Flag, SDValue Chain,

196 getTargetNode(N, Ty, DAG, Flag));

197 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);

198 }

199

200

201

202

203

204 template

207 unsigned LoFlag, SDValue Chain,

210 getTargetNode(N, Ty, DAG, HiFlag));

213 getTargetNode(N, Ty, DAG, LoFlag));

215 }

216

217

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221

222

223 template

232

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238

239

240 template

245

247 DAG.getNode(MipsISD::Highest, DL, Ty,

252 DAG.getNode(MipsISD::Higher, DL, Ty, Higher));

258

261 }

262

263

264

265

266

267 template

273 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),

275 }

276

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280

281 template

291

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294

295

296 template

303

304

305

306

307 virtual void

309 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,

310 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,

311 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,

313

314 protected:

317

318

320

322

323 private:

324

326 unsigned Flag) const;

327

328

330 unsigned Flag) const;

331

332

334 unsigned Flag) const;

335

336

338 unsigned Flag) const;

339

340

342 unsigned Flag) const;

343

344

351

352

367 bool HasExtractInsert) const;

369 bool HasExtractInsert) const;

377 bool IsSRA) const;

382

383

384

385 virtual bool

386 isEligibleForTailCallOptimization(const CCState &CCInfo,

387 unsigned NextStackOffset,

389

390

391

392

394 std::vector &OutChains, SelectionDAG &DAG,

397 const Argument *FuncArg, unsigned FirstReg,

400

401

403 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,

406 unsigned FirstReg, unsigned LastReg,

409

410

411

412

413 void writeVarArgRegs(std::vector &OutChains, SDValue Chain,

416

422

426

429

431 bool isVarArg,

434

439

442

443 bool shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const override;

444

445

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452

453

454

455 std::pair<unsigned, const TargetRegisterClass *>

456 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;

457

458 std::pair<unsigned, const TargetRegisterClass *>

460 StringRef Constraint, MVT VT) const override;

461

462

463

464

465

467 std::vector &Ops,

469

471 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {

472 if (ConstraintCode == "o")

474 if (ConstraintCode == "R")

476 if (ConstraintCode == "ZC")

479 }

480

482 Type *Ty, unsigned AS,

484

486

488 const AttributeList &FuncAttributes) const override;

489

490

491

492

493 bool isFPImmLegal(const APFloat &Imm, EVT VT,

494 bool ForCodeSize) const override;

495

496 bool isLegalICmpImmediate(int64_t Imm) const override;

498

503

504 bool shouldInsertFencesForAtomic(const Instruction *I) const override {

505 return true;

506 }

507

508

509 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,

510 MachineBasicBlock *BB,

511 unsigned Size, unsigned DstReg,

512 unsigned SrcRec) const;

513

514 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,

515 MachineBasicBlock *BB) const;

516 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,

517 MachineBasicBlock *BB,

518 unsigned Size) const;

519 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,

520 MachineBasicBlock *BB) const;

521 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,

522 MachineBasicBlock *BB,

523 unsigned Size) const;

524 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;

525 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,

526 bool isFPCmp, unsigned Opc) const;

527 MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,

528 MachineBasicBlock *BB) const;

529 MachineBasicBlock *emitLDR_W(MachineInstr &MI, MachineBasicBlock *BB) const;

530 MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const;

531 MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const;

532 MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const;

533 };

534

535

542

543namespace Mips {

544

545FastISel *createFastISel(FunctionLoweringInfo &funcInfo,

546 const TargetLibraryInfo *libInfo);

547

548}

549

550}

551

552#endif

amdgpu aa AMDGPU Address space based Alias Analysis Wrapper

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static bool isLegalAddImmediate(const TargetTransformInfo &TTI, Immediate Offset)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This file describes how to lower LLVM code to machine code.

This class represents an incoming formal argument to a Function.

CCState - This class holds information needed while lowering arguments and return values.

CCValAssign - Represent assignment of one arg/retval to a location.

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...

FunctionLoweringInfo - This contains information that is global to a function that is used when lower...

This is an important class for using LLVM in a threaded context.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Representation of each machine instruction.

MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...

Definition MipsISelLowering.h:58

If a physical register, this returns the register that receives the exception typeid on entry to a la...

Definition MipsISelLowering.h:151

MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...

bool hasBitTest(SDValue X, SDValue Y) const override

Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...

static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)

If a physical register, this returns the register that receives the exception address on entry to an ...

Definition MipsISelLowering.h:144

SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const

Definition MipsISelLowering.h:268

unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override

Break down vectors to the correct number of gpr sized integers.

Return the register ID of the name passed in.

SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const

Definition MipsISelLowering.h:241

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition MipsISelLowering.h:73

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

getSetCCResultType - get the ISD::SETCC result ValueType

SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const

Definition MipsISelLowering.h:192

FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override

createFastISel - This method returns a target specific FastISel object, or null if the target does no...

MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

const MipsABIInfo & ABI

Definition MipsISelLowering.h:321

SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const

Definition MipsISelLowering.h:205

SDValue getDllimportVariable(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, SDValue Chain, const MachinePointerInfo &PtrInfo) const

Definition MipsISelLowering.h:297

bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override

Return true if it is profitable to fold a pair of shifts into a mask.

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

CCAssignFn * CCAssignFnForReturn() const

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

SDValue getDllimportSymbol(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const

Definition MipsISelLowering.h:282

CCAssignFn * CCAssignFnForCall() const

unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...

SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const

Definition MipsISelLowering.h:224

SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const

void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const

This function fills Ops, which is the list of operands that will later be used when a function call n...

EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

bool isCheapToSpeculateCtlz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

LowerOperation - Provide custom lowering hooks for some operations.

bool isCheapToSpeculateCttz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const

Definition MipsISelLowering.h:173

bool softPromoteHalfType() const override

Definition MipsISelLowering.h:155

SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const

const MipsSubtarget & Subtarget

Definition MipsISelLowering.h:319

ISD::NodeType getExtendForAtomicOps() const override

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...

Definition MipsISelLowering.h:110

void HandleByVal(CCState *, unsigned &, Align) const override

Target-specific cleanup for formal ByVal parameters.

bool isJumpTableRelative() const override

Definition MipsISelLowering.h:157

SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const

Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const override

Return the correct alignment for the current calling convention.

Definition MipsISelLowering.h:102

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

LLVM_ABI SDVTList getVTList(EVT VT)

Return an SDVTList that represents the list of values specified.

LLVM_ABI SDValue getRegister(Register Reg, EVT VT)

LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)

Loads are not normal binary operators: their result type is not determined by their operands,...

LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

MachineFunction & getMachineFunction() const

SDValue getEntryNode() const

Return the token chain corresponding to the entry of the function.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

Provides information about what library functions are available for the current target.

const TargetMachine & getTargetMachine() const

virtual bool useSoftFloat() const

virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const

TargetLowering(const TargetLowering &)=delete

virtual unsigned getJumpTableEncoding() const

Return the entry encoding for a jump table in the current function.

bool isPositionIndependent() const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

bool isVectorTy() const

True if this is an instance of VectorType.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

@ ADD

Simple integer binary arithmetic operators.

@ SIGN_EXTEND

Conversion operators.

@ SHL

Shift and rotation operations.

FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)

This is an optimization pass for GlobalISel generic memory operations.

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

Create MipsTargetLowering objects.

DWARFExpression::Operation Op

const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)

This struct is a compact representation of a valid (non-zero power of two) alignment.

This class contains a discriminated union of information about pointers in memory operands,...

static LLVM_ABI MachinePointerInfo getGOT(MachineFunction &MF)

Return a MachinePointerInfo record that refers to a GOT entry.

This contains information for each constraint that we are lowering.

This structure contains all information that is necessary for lowering calls.