MipsInstrInfo.h Source File (original) (raw)

17#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H

18#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H

28#include

30#define GET_INSTRINFO_HEADER

31#include "MipsGenInstrInfo.inc"

33namespace llvm {

35class MachineInstr;

36class MachineOperand;

37class MipsSubtarget;

38class TargetRegisterClass;

39class TargetRegisterInfo;

42 virtual void anchor();

44protected:

48public:

69 bool AllowModify) const override;

72 int *BytesRemoved = nullptr) const override;

77 int *BytesAdded = nullptr) const override;

79 bool

85 bool AllowModify,

93 int64_t BrOffset) const override;

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163 virtual void

165 Register SrcReg, bool isKill, int FrameIndex,

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184 unsigned &SrcOpIdx2) const override;

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188 StringRef &ErrInfo) const override;

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190 std::pair<unsigned, unsigned>

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199 std::optional

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209 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;

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211 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,

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217};

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223namespace Mips {

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238}

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240}

241

242#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Instances of this class represent a single low-level machine instruction.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

A description of a memory reference used in the backend.

Flags

Flags values. These may be or'd together.

MachineOperand class - Representation of each machine instruction operand.

Definition MipsInstrInfo.h:41

MCInst getNop() const override

bool SafeAfterMflo(const MachineInstr &MI) const

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition MipsInstrInfo.h:148

bool SafeInForbiddenSlot(const MachineInstr &MI) const

Predicate to determine if an instruction can go in a forbidden slot.

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

Return the number of bytes of code the specified instruction may be.

MachineInstrBuilder insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const

Insert an ISA appropriate nop.

bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override

Determine if the branch target is in range.

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Branch Analysis.

const MipsSubtarget & Subtarget

Definition MipsInstrInfo.h:45

MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const

MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const

Create an instruction which has the same operands and memory operands as MI but has a new opcode.

virtual bool isBranchWithImm(unsigned Opc) const

Definition MipsInstrInfo.h:141

bool HasForbiddenSlot(const MachineInstr &MI) const

Predicate to determine if an instruction has a forbidden slot.

bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const

Predicate to determine if an instruction can go in an FPU delay slot.

bool isZeroImm(const MachineOperand &op) const

unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const

Determine the opcode of a non-delay slot form for a branch if one exists.

bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const

Predicate to determine if an instruction can go in a load delay slot.

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition MipsInstrInfo.h:155

virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const =0

std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override

unsigned UncondBrOpc

Definition MipsInstrInfo.h:46

bool HasFPUDelaySlot(const MachineInstr &MI) const

Predicate to determine if an instruction has an FPU delay slot.

const MipsRegisterInfo & getRegisterInfo() const

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

Definition MipsInstrInfo.h:134

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

Perform target specific instruction verification.

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

BranchType

Definition MipsInstrInfo.h:49

@ BT_Uncond

Definition MipsInstrInfo.h:52

@ BT_NoBranch

Definition MipsInstrInfo.h:51

@ BT_None

Definition MipsInstrInfo.h:50

@ BT_Cond

Definition MipsInstrInfo.h:53

@ BT_CondUncond

Definition MipsInstrInfo.h:54

@ BT_Indirect

Definition MipsInstrInfo.h:55

virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0

static const MipsInstrInfo * create(MipsSubtarget &STI)

bool IsMfloOrMfhi(const MachineInstr &MI) const

bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override

virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const =0

MipsInstrInfo(const MipsSubtarget &STI, const MipsRegisterInfo &RI, unsigned UncondBrOpc)

virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0

bool HasLoadDelaySlot(const MachineInstr &MI) const

Predicate to determine if an instruction has a load delay slot.

bool isAsCheapAsAMove(const MachineInstr &MI) const override

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

Insert nop instruction when hazard condition is found.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

const TargetRegisterInfo & getRegisterInfo() const