LLVM: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Source File (original) (raw)

49

50 static const struct {

53 } RegMap[] = {

54 {codeview::RegisterId::MIPS_ZERO, Mips::ZERO},

55 {codeview::RegisterId::MIPS_AT, Mips::AT},

56 {codeview::RegisterId::MIPS_V0, Mips::V0},

57 {codeview::RegisterId::MIPS_V1, Mips::V1},

58 {codeview::RegisterId::MIPS_A0, Mips::A0},

59 {codeview::RegisterId::MIPS_A1, Mips::A1},

60 {codeview::RegisterId::MIPS_A2, Mips::A2},

61 {codeview::RegisterId::MIPS_A3, Mips::A3},

62 {codeview::RegisterId::MIPS_T0, Mips::T0},

63 {codeview::RegisterId::MIPS_T1, Mips::T1},

64 {codeview::RegisterId::MIPS_T2, Mips::T2},

65 {codeview::RegisterId::MIPS_T3, Mips::T3},

66 {codeview::RegisterId::MIPS_T4, Mips::T4},

67 {codeview::RegisterId::MIPS_T5, Mips::T5},

68 {codeview::RegisterId::MIPS_T6, Mips::T6},

69 {codeview::RegisterId::MIPS_T7, Mips::T7},

70 {codeview::RegisterId::MIPS_S0, Mips::S0},

71 {codeview::RegisterId::MIPS_S1, Mips::S1},

72 {codeview::RegisterId::MIPS_S2, Mips::S2},

73 {codeview::RegisterId::MIPS_S3, Mips::S3},

74 {codeview::RegisterId::MIPS_S4, Mips::S4},

75 {codeview::RegisterId::MIPS_S5, Mips::S5},

76 {codeview::RegisterId::MIPS_S6, Mips::S6},

77 {codeview::RegisterId::MIPS_S7, Mips::S7},

78 {codeview::RegisterId::MIPS_T8, Mips::T8},

79 {codeview::RegisterId::MIPS_T9, Mips::T9},

80 {codeview::RegisterId::MIPS_K0, Mips::K0},

81 {codeview::RegisterId::MIPS_K1, Mips::K1},

82 {codeview::RegisterId::MIPS_GP, Mips::GP},

83 {codeview::RegisterId::MIPS_SP, Mips::SP},

84 {codeview::RegisterId::MIPS_S8, Mips::FP},

85 {codeview::RegisterId::MIPS_RA, Mips::RA},

86 {codeview::RegisterId::MIPS_LO, Mips::HI0},

87 {codeview::RegisterId::MIPS_HI, Mips::LO0},

88 {codeview::RegisterId::MIPS_Fir, Mips::FCR0},

89 {codeview::RegisterId::MIPS_Psr, Mips::COP012},

90 {codeview::RegisterId::MIPS_F0, Mips::F0},

91 {codeview::RegisterId::MIPS_F1, Mips::F1},

92 {codeview::RegisterId::MIPS_F2, Mips::F2},

93 {codeview::RegisterId::MIPS_F3, Mips::F3},

94 {codeview::RegisterId::MIPS_F4, Mips::F4},

95 {codeview::RegisterId::MIPS_F5, Mips::F5},

96 {codeview::RegisterId::MIPS_F6, Mips::F6},

97 {codeview::RegisterId::MIPS_F7, Mips::F7},

98 {codeview::RegisterId::MIPS_F8, Mips::F8},

99 {codeview::RegisterId::MIPS_F9, Mips::F9},

100 {codeview::RegisterId::MIPS_F10, Mips::F10},

101 {codeview::RegisterId::MIPS_F11, Mips::F11},

102 {codeview::RegisterId::MIPS_F12, Mips::F12},

103 {codeview::RegisterId::MIPS_F13, Mips::F13},

104 {codeview::RegisterId::MIPS_F14, Mips::F14},

105 {codeview::RegisterId::MIPS_F15, Mips::F15},

106 {codeview::RegisterId::MIPS_F16, Mips::F16},

107 {codeview::RegisterId::MIPS_F17, Mips::F17},

108 {codeview::RegisterId::MIPS_F18, Mips::F18},

109 {codeview::RegisterId::MIPS_F19, Mips::F19},

110 {codeview::RegisterId::MIPS_F20, Mips::F20},

111 {codeview::RegisterId::MIPS_F21, Mips::F21},

112 {codeview::RegisterId::MIPS_F22, Mips::F22},

113 {codeview::RegisterId::MIPS_F23, Mips::F23},

114 {codeview::RegisterId::MIPS_F24, Mips::F24},

115 {codeview::RegisterId::MIPS_F25, Mips::F25},

116 {codeview::RegisterId::MIPS_F26, Mips::F26},

117 {codeview::RegisterId::MIPS_F27, Mips::F27},

118 {codeview::RegisterId::MIPS_F28, Mips::F28},

119 {codeview::RegisterId::MIPS_F29, Mips::F29},

120 {codeview::RegisterId::MIPS_F30, Mips::F30},

121 {codeview::RegisterId::MIPS_F31, Mips::F31},

122 {codeview::RegisterId::MIPS_Fsr, Mips::FCR31},

123 };

124 for (const auto &I : RegMap)

125 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));

126}

137 if (CPU.empty() || CPU == "generic") {

139 if (TT.isMIPS32())

140 CPU = "mips32r6";

141 else

142 CPU = "mips64r6";

143 } else {

144 if (TT.isMIPS32())

145 CPU = "mips32";

146 else

147 CPU = "mips64";

148 }

149 }

150 return CPU;

151}

155 InitMipsMCInstrInfo(X);

156 return X;

157}

161 InitMipsMCRegisterInfo(X, Mips::RA);

162 return X;

163}

168 return createMipsMCSubtargetInfoImpl(TT, CPU, CPU, FS);

169}

175

176 if (TT.isOSBinFormatCOFF())

178 else

180

181 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);

184

185 return MAI;

186}

189 unsigned SyntaxVariant,

194}

197 std::unique_ptr &&MAB,

198 std::unique_ptr &&OW,

199 std::unique_ptr &&Emitter) {

203 return S;

204}

219 return new MipsWinCOFFTargetStreamer(S);

221}

255 return new MipsMCInstrAnalysis(Info);

256}

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295 }

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303}