LLVM: lib/Target/NVPTX/NVPTXInstrInfo.cpp Source File (original) (raw)
1
2
3
4
5
6
7
8
9
10
11
12
19
20using namespace llvm;
21
22#define GET_INSTRINFO_CTOR_DTOR
23#include "NVPTXGenInstrInfo.inc"
24
25
26void NVPTXInstrInfo::anchor() {}
27
30
34 Register SrcReg, bool KillSrc,
35 bool RenamableDest, bool RenamableSrc) const {
39
40 if (DestRC != SrcRC)
41 report_fatal_error("Copy one register into another with a different width");
42
43 unsigned Op;
44 if (DestRC == &NVPTX::B1RegClass)
45 Op = NVPTX::MOV_B1_r;
46 else if (DestRC == &NVPTX::B16RegClass)
47 Op = NVPTX::MOV_B16_r;
48 else if (DestRC == &NVPTX::B32RegClass)
49 Op = NVPTX::MOV_B32_r;
50 else if (DestRC == &NVPTX::B64RegClass)
51 Op = NVPTX::MOV_B64_r;
52 else if (DestRC == &NVPTX::B128RegClass)
53 Op = NVPTX::MOV_B128_r;
54 else
56
59}
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
88 bool AllowModify) const {
89
91 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I))
92 return false;
93
94
96
97
98 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
99 if (LastInst.getOpcode() == NVPTX::GOTO) {
101 return false;
102 } else if (LastInst.getOpcode() == NVPTX::CBranch) {
103
106 return false;
107 }
108
109 return true;
110 }
111
112
114
115
116 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
117 return true;
118
119
120 if (SecondLastInst.getOpcode() == NVPTX::CBranch &&
121 LastInst.getOpcode() == NVPTX::GOTO) {
125 return false;
126 }
127
128
129
130 if (SecondLastInst.getOpcode() == NVPTX::GOTO &&
131 LastInst.getOpcode() == NVPTX::GOTO) {
133 I = LastInst;
134 if (AllowModify)
135 I->eraseFromParent();
136 return false;
137 }
138
139
140 return true;
141}
142
144 int *BytesRemoved) const {
145 assert(!BytesRemoved && "code size not handled");
148 return 0;
149 --I;
150 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
151 return 0;
152
153
154 I->eraseFromParent();
155
157
159 return 1;
160 --I;
161 if (I->getOpcode() != NVPTX::CBranch)
162 return 1;
163
164
165 I->eraseFromParent();
166 return 2;
167}
168
174 int *BytesAdded) const {
175 assert(!BytesAdded && "code size not handled");
176
177
178 assert(TBB && "insertBranch must not be told to insert a fallthrough");
180 "NVPTX branch conditions have two components!");
181
182
183 if (!FBB) {
184 if (Cond.empty())
186 else
188 return 1;
189 }
190
191
194 return 2;
195}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineInstrBundleIterator< MachineInstr > iterator
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineBasicBlock * getMBB() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition NVPTXInstrInfo.cpp:169
NVPTXInstrInfo(const NVPTXSubtarget &STI)
Definition NVPTXInstrInfo.cpp:28
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition NVPTXInstrInfo.cpp:143
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
Definition NVPTXInstrInfo.cpp:84
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Definition NVPTXInstrInfo.cpp:31
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
unsigned getKillRegState(bool B)
DWARFExpression::Operation Op