NVPTXTargetMachine.cpp Source File (original) (raw)

27#include "llvm/IR/IntrinsicsNVPTX.h"

39#include

40#include

41#include

43using namespace llvm;

49 cl::desc("Disable load/store vectorizer"),

54 "disable-nvptx-require-structured-cfg",

55 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "

56 "structured CFG. The requirement should be disabled only when "

57 "unexpected regressions happen."),

61 "nvptx-short-ptr",

63 "Use 32-bit pointers for accessing const/local/shared address spaces."),

85 "nvptx-early-byval-copy",

86 cl::desc("Create a copy of byval function arguments early."),

89namespace llvm {

106

107}

108

110

113

115

116

132}

133

135 std::string Ret = "e";

136

138 Ret += "-p:32:32";

139 else if (UseShortPointers)

140 Ret += "-p3:32:32-p4:32:32-p5:32:32";

141

142 Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";

143

144 return Ret;

145}

146

150 std::optionalReloc::Model RM,

151 std::optionalCodeModel::Model CM,

153

154

157 TT, CPU, FS, Options, Reloc::PIC_,

161 StrPool(StrAlloc) {

164 else

169}

170

172

173void NVPTXTargetMachine32::anchor() {}

174

178 std::optionalReloc::Model RM,

179 std::optionalCodeModel::Model CM,

182

183void NVPTXTargetMachine64::anchor() {}

184

188 std::optionalReloc::Model RM,

189 std::optionalCodeModel::Model CM,

192

193namespace {

194

196public:

199

201 return getTM();

202 }

203

204 void addIRPasses() override;

205 bool addInstSelector() override;

206 void addPreRegAlloc() override;

207 void addPostRegAlloc() override;

208 void addMachineSSAOptimization() override;

209

210 FunctionPass *createTargetRegisterAllocator(bool) override;

211 void addFastRegAlloc() override;

212 void addOptimizedRegAlloc() override;

213

214 bool addRegAssignAndRewriteFast() override {

216 }

217

218 bool addRegAssignAndRewriteOptimized() override {

220 }

221

222private:

223

224

225 void addEarlyCSEOrGVNPass();

226

227

228 void addAddressSpaceInferencePasses();

229

230

231 void addStraightLineScalarOptimizationPasses();

232};

233

234}

235

237 return new NVPTXPassConfig(*this, PM);

238}

239

243 return NVPTXMachineFunctionInfo::create(Allocator,

245}

246

249}

250

252#define GET_PASS_REGISTRY "NVPTXPassRegistry.def"

254

258

259

262

263

268 });

269}

270

274}

275

276std::pair<const Value *, unsigned>

278 if (auto *II = dyn_cast(V)) {

279 switch (II->getIntrinsicID()) {

280 case Intrinsic::nvvm_isspacep_const:

282 case Intrinsic::nvvm_isspacep_global:

284 case Intrinsic::nvvm_isspacep_local:

286 case Intrinsic::nvvm_isspacep_shared:

287 case Intrinsic::nvvm_isspacep_shared_cluster:

289 default:

290 break;

291 }

292 }

293 return std::make_pair(nullptr, -1);

294}

295

296void NVPTXPassConfig::addEarlyCSEOrGVNPass() {

299 else

301}

302

303void NVPTXPassConfig::addAddressSpaceInferencePasses() {

304

305

308

309

312}

313

314void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {

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321

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323 addEarlyCSEOrGVNPass();

324

326

327

329}

330

331void NVPTXPassConfig::addIRPasses() {

332

333

334

335

336

348

352 AAR.addAAResult(WrapperPass->getResult());

353 }));

354

355

356

357

358

359 const NVPTXSubtarget &ST = *getTM().getSubtargetImpl();

361

366

367

368

371 addAddressSpaceInferencePasses();

372 addStraightLineScalarOptimizationPasses();

373 }

374

378

379

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384

385

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387

388

389

390

391

392

394 addEarlyCSEOrGVNPass();

398 }

399

400 if (ST.hasPTXASUnreachableBug()) {

401

402

403 const auto &Options = getNVPTXTargetMachine().Options;

405 Options.NoTrapAfterNoreturn));

406 }

407}

408

409bool NVPTXPassConfig::addInstSelector() {

414

415 return false;

416}

417

418void NVPTXPassConfig::addPreRegAlloc() {

419

421}

422

423void NVPTXPassConfig::addPostRegAlloc() {

426

427

428

430 }

431}

432

433FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {

434 return nullptr;

435}

436

437void NVPTXPassConfig::addFastRegAlloc() {

440}

441

442void NVPTXPassConfig::addOptimizedRegAlloc() {

447

450

451

453 printAndVerify("After Machine Scheduling");

454

456

457

458

459

460 printAndVerify("After StackSlotColoring");

461}

462

463void NVPTXPassConfig::addMachineSSAOptimization() {

464

466 printAndVerify("After Pre-RegAlloc TailDuplicate");

467

468

469

471

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475

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477

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480

481

482

483

485 printAndVerify("After codegen DCE pass");

486

487

488

489

490 if (addILPOpts())

491 printAndVerify("After ILP optimizations");

492

495

497 printAndVerify("After Machine LICM, CSE and Sinking passes");

498

500 printAndVerify("After codegen peephole optimization pass");

501}

#define LLVM_EXTERNAL_VISIBILITY

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

This file provides the interface for LLVM's Global Value Numbering pass which eliminates fully redund...

static std::string computeDataLayout()

This is the NVPTX address space based alias analysis pass.

static cl::opt< bool > DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer", cl::desc("Disable load/store vectorizer"), cl::init(false), cl::Hidden)

static cl::opt< bool > DisableRequireStructuredCFG("disable-nvptx-require-structured-cfg", cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " "structured CFG. The requirement should be disabled only when " "unexpected regressions happen."), cl::init(false), cl::Hidden)

static cl::opt< bool > UseShortPointersOpt("nvptx-short-ptr", cl::desc("Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden)

static cl::opt< bool > EarlyByValArgsCopy("nvptx-early-byval-copy", cl::desc("Create a copy of byval function arguments early."), cl::init(false), cl::Hidden)

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget()

This file a TargetTransformInfo::Concept conforming object specific to the NVPTX target machine.

uint64_t IntrinsicInst * II

static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

static bool is64Bit(const char *name)

A manager for alias analyses.

void registerFunctionAnalysis()

void addAAResult(AAResultT &AAResult)

Allocate memory in an ever growing pool, as if by bump-pointer.

implements a set of functionality in the TargetMachine class for targets that make use of the indepen...

FunctionPass class - This class is used to implement most global optimizations.

Legacy wrapper pass to provide the NVPTXAAResult object.

Analysis pass providing a never-invalidated alias analysis result.

unsigned int getSmVersion() const

bool hasTargetName() const

NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

void registerDefaultAliasAnalyses(AAManager &AAM) override

Allow the target to register alias analyses with the AAManager for use with the new pass manager.

std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override

If the specified predicate checks whether a generic pointer falls within a specified address space,...

void registerPassBuilderCallbacks(PassBuilder &PB) override

Allow the target to modify the pass pipeline.

~NVPTXTargetMachine() override

NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OP, bool is64bit)

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

This class provides access to building LLVM's passes.

void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)

LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v< PassT, PassManager > > addPass(PassT &&Pass)

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Pass interface - Implemented by all 'passes'.

StringRef - Represent a constant reference to a string, i.e.

void setRequiresStructuredCFG(bool Value)

std::unique_ptr< const MCSubtargetInfo > STI

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

LLVM Value Representation.

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

Interfaces for registering analysis passes, producing common pass manager configurations,...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

void initializeNVPTXLowerAllocaPass(PassRegistry &)

char & EarlyMachineLICMID

This pass performs loop invariant code motion on machine instructions.

ModulePass * createNVPTXAssignValidGlobalNamesPass()

MachineFunctionPass * createNVPTXReplaceImageHandlesPass()

FunctionPass * createNVPTXLowerUnreachablePass(bool TrapUnreachable, bool NoTrapAfterNoreturn)

void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &)

Pass * createLoadStoreVectorizerPass()

Create a legacy pass manager instance of the LoadStoreVectorizer pass.

ModulePass * createExpandVariadicsPass(ExpandVariadicsMode)

char & RegisterCoalescerID

RegisterCoalescer - This pass merges live ranges to eliminate copies.

ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)

A function to deduce a function pass type and wrap it in the templated adaptor.

ModulePass * createGenericToNVVMLegacyPass()

FunctionPass * createNVVMReflectPass(unsigned int SmVersion)

void initializeNVPTXLowerAggrCopiesPass(PassRegistry &)

void initializeNVPTXExternalAAWrapperPass(PassRegistry &)

char & MachineSinkingID

MachineSinking - This pass performs sinking on machine instructions.

MachineFunctionPass * createNVPTXPrologEpilogPass()

MachineFunctionPass * createNVPTXProxyRegErasurePass()

char & TailDuplicateLegacyID

TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.

FunctionPass * createNaryReassociatePass()

char & PatchableFunctionID

This pass implements the "patchable-function" attribute.

char & PostRASchedulerID

PostRAScheduler - This pass performs post register allocation scheduling.

char & RemoveLoadsIntoFakeUsesID

RemoveLoadsIntoFakeUses pass.

MachineFunctionPass * createNVPTXPeephole()

void initializeNVVMReflectPass(PassRegistry &)

char & MachineSchedulerID

MachineScheduler - This pass schedules machine instructions.

char & PeepholeOptimizerLegacyID

PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...

FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOptLevel OptLevel)

createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG,...

char & PrologEpilogCodeInserterID

PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...

void initializeGenericToNVVMLegacyPassPass(PassRegistry &)

void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &)

void initializeNVPTXLowerUnreachablePass(PassRegistry &)

void initializeNVPTXLowerArgsPass(PassRegistry &)

char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

FunctionPass * createNVPTXLowerArgsPass()

CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)

Helper method for getting the code model, returning Default if CM does not have a value.

char & ShrinkWrapID

ShrinkWrap pass. Look for the best place to insert save and restore.

char & MachineLateInstrsCleanupID

MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...

void initializeNVPTXAAWrapperPassPass(PassRegistry &)

FunctionPass * createNVPTXImageOptimizerPass()

FunctionPass * createNVPTXLowerAllocaPass()

char & OptimizePHIsLegacyID

OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...

FunctionPass * createSpeculativeExecutionPass()

char & StackMapLivenessID

StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...

char & FuncletLayoutID

This pass lays out funclets contiguously.

FunctionPass * createAllocaHoisting()

void initializeNVVMIntrRangePass(PassRegistry &)

char & PostRAMachineSinkingID

This pass perform post-ra machine sink for COPY instructions.

CodeGenOptLevel

Code generation optimization level.

char & StackSlotColoringID

StackSlotColoring - This pass performs stack slot coloring.

FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)

FunctionPass * createLowerAggrCopies()

char & ProcessImplicitDefsID

ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.

FunctionPass * createGVNPass()

Create a legacy GVN pass.

FunctionPass * createNVPTXAtomicLowerPass()

ModulePass * createNVPTXCtorDtorLoweringLegacyPass()

char & MachineCSELegacyID

MachineCSE - This pass performs global CSE on machine instructions.

char & LiveVariablesID

LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...

char & EarlyTailDuplicateLegacyID

Duplicate blocks with unconditional branches into tails of their predecessors.

void initializeNVPTXAllocaHoistingPass(PassRegistry &)

Target & getTheNVPTXTarget64()

char & StackColoringLegacyID

StackSlotColoring - This pass performs stack coloring and merging.

FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)

void initializeNVPTXProxyRegErasurePass(PassRegistry &)

ImmutablePass * createNVPTXAAWrapperPass()

ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)

A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...

char & TwoAddressInstructionPassID

TwoAddressInstruction - This pass reduces two-address instructions to use two operands.

FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

char & LocalStackSlotAllocationID

LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...

FunctionPass * createStraightLineStrengthReducePass()

FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)

char & PHIEliminationID

PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.

FunctionPass * createSROAPass(bool PreserveCFG=true)

void initializeNVPTXAtomicLowerPass(PassRegistry &)

char & MachineCopyPropagationID

MachineCopyPropagation - This pass performs copy propagation on machine instructions.

char & DeadMachineInstructionElimID

DeadMachineInstructionElim - This pass removes dead machine instructions.

Target & getTheNVPTXTarget32()

void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &)

Implement std::hash so that hash_code can be used in STL containers.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

RegisterTargetMachine - Helper template for registering a target machine implementation,...