NVPTXTargetMachine.cpp Source File (original) (raw)

28#include "llvm/IR/IntrinsicsNVPTX.h"

41#include

42#include

43#include

45using namespace llvm;

51 cl::desc("Disable load/store vectorizer"),

58 cl::desc("Disable NVPTX IR Peephole"),

63 "disable-nvptx-require-structured-cfg",

64 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "

65 "structured CFG. The requirement should be disabled only when "

66 "unexpected regressions happen."),

70 "nvptx-short-ptr",

72 "Use 32-bit pointers for accessing const/local/shared address spaces."),

94 "nvptx-early-byval-copy",

95 cl::desc("Create a copy of byval function arguments early."),

128

132 std::optionalReloc::Model RM,

133 std::optionalCodeModel::Model CM,

135

136

142 Subtarget(TT, std::string(CPU), std::string(FS), *this),

143 StrPool(StrAlloc) {

146 else

151}

152

154

155void NVPTXTargetMachine32::anchor() {}

156

160 std::optionalReloc::Model RM,

161 std::optionalCodeModel::Model CM,

164

165void NVPTXTargetMachine64::anchor() {}

166

170 std::optionalReloc::Model RM,

171 std::optionalCodeModel::Model CM,

174

175namespace {

176

178public:

181

184 }

185

186 void addIRPasses() override;

187 bool addInstSelector() override;

188 void addPreRegAlloc() override;

189 void addPostRegAlloc() override;

190 void addMachineSSAOptimization() override;

191

192 FunctionPass *createTargetRegisterAllocator(bool) override;

193 void addFastRegAlloc() override;

194 void addOptimizedRegAlloc() override;

195

196 bool addRegAssignAndRewriteFast() override {

198 }

199

200 bool addRegAssignAndRewriteOptimized() override {

202 }

203

204private:

205

206

207 void addEarlyCSEOrGVNPass();

208

209

210 void addAddressSpaceInferencePasses();

211

212

213 void addStraightLineScalarOptimizationPasses();

214};

215

216}

217

219 return new NVPTXPassConfig(*this, PM);

220}

221

228

232

234#define GET_PASS_REGISTRY "NVPTXPassRegistry.def"

236

237 PB.registerPipelineStartEPCallback(

239

240

241 if (Subtarget.hasTargetName())

243

245

246

251 });

252

254 PB.registerFullLinkTimeOptimizationLastEPCallback(

259 });

260 }

261}

262

267

268std::pair<const Value *, unsigned>

271 switch (II->getIntrinsicID()) {

272 case Intrinsic::nvvm_isspacep_const:

274 case Intrinsic::nvvm_isspacep_global:

276 case Intrinsic::nvvm_isspacep_local:

278 case Intrinsic::nvvm_isspacep_shared:

280 case Intrinsic::nvvm_isspacep_shared_cluster:

281 return std::make_pair(II->getArgOperand(0),

283 default:

284 break;

285 }

286 }

287 return std::make_pair(nullptr, -1);

288}

289

290void NVPTXPassConfig::addEarlyCSEOrGVNPass() {

293 else

295}

296

297void NVPTXPassConfig::addAddressSpaceInferencePasses() {

298

299

302

303

306}

307

308void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {

311

312

314

315

316

317 addEarlyCSEOrGVNPass();

318

320

321

323}

324

325void NVPTXPassConfig::addIRPasses() {

326

327

328

329

330

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357

358

359

362 addAddressSpaceInferencePasses();

363 addStraightLineScalarOptimizationPasses();

364 }

365

369

370

372

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374

375

376

377

378

379

380

381

382

383

385 addEarlyCSEOrGVNPass();

392 }

393

394 if (ST.hasPTXASUnreachableBug()) {

395

396

397 const auto &Options = getNVPTXTargetMachine().Options;

399 Options.NoTrapAfterNoreturn));

400 }

401}

402

403bool NVPTXPassConfig::addInstSelector() {

408

409 return false;

410}

411

412void NVPTXPassConfig::addPreRegAlloc() {

414

416}

417

418void NVPTXPassConfig::addPostRegAlloc() {

421

422

423

425 }

426}

427

428FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {

429 return nullptr;

430}

431

432void NVPTXPassConfig::addFastRegAlloc() {

435}

436

437void NVPTXPassConfig::addOptimizedRegAlloc() {

442

445

446

448 printAndVerify("After Machine Scheduling");

449

451

452

453

454

455 printAndVerify("After StackSlotColoring");

456}

457

458void NVPTXPassConfig::addMachineSSAOptimization() {

459

461 printAndVerify("After Pre-RegAlloc TailDuplicate");

462

463

464

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467

468

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475

476

477

478

480 printAndVerify("After codegen DCE pass");

481

482

483

484

485 if (addILPOpts())

486 printAndVerify("After ILP optimizations");

487

490

492 printAndVerify("After Machine LICM, CSE and Sinking passes");

493

495 printAndVerify("After codegen peephole optimization pass");

496}

#define LLVM_EXTERNAL_VISIBILITY

This file provides the interface for LLVM's Global Value Numbering pass which eliminates fully redund...

This is the NVPTX address space based alias analysis pass.

static cl::opt< bool > DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer", cl::desc("Disable load/store vectorizer"), cl::init(false), cl::Hidden)

static cl::opt< bool > DisableRequireStructuredCFG("disable-nvptx-require-structured-cfg", cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " "structured CFG. The requirement should be disabled only when " "unexpected regressions happen."), cl::init(false), cl::Hidden)

static cl::opt< bool > UseShortPointersOpt("nvptx-short-ptr", cl::desc("Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden)

static cl::opt< bool > EarlyByValArgsCopy("nvptx-early-byval-copy", cl::desc("Create a copy of byval function arguments early."), cl::init(false), cl::Hidden)

static cl::opt< bool > DisableNVPTXIRPeephole("disable-nvptx-ir-peephole", cl::desc("Disable NVPTX IR Peephole"), cl::init(false), cl::Hidden)

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget()

Definition NVPTXTargetMachine.cpp:98

This file a TargetTransformInfoImplBase conforming object specific to the NVPTX target machine.

uint64_t IntrinsicInst * II

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

const GCNTargetMachine & getTM(const GCNSubtarget *STI)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

A manager for alias analyses.

void registerFunctionAnalysis()

CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)

FunctionPass class - This class is used to implement most global optimizations.

const TargetSubtargetInfo * getSubtargetImpl(const Function &) const override

Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...

Analysis pass providing a never-invalidated alias analysis result.

NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Definition NVPTXTargetMachine.cpp:157

NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Definition NVPTXTargetMachine.cpp:167

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

Definition NVPTXTargetMachine.cpp:264

std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override

If the specified predicate checks whether a generic pointer falls within a specified address space,...

Definition NVPTXTargetMachine.cpp:269

void registerPassBuilderCallbacks(PassBuilder &PB) override

Allow the target to modify the pass pipeline.

Definition NVPTXTargetMachine.cpp:233

void registerEarlyDefaultAliasAnalyses(AAManager &AAM) override

Allow the target to register early alias analyses (AA before BasicAA) with the AAManager for use with...

Definition NVPTXTargetMachine.cpp:229

~NVPTXTargetMachine() override

NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OP, bool is64bit)

Definition NVPTXTargetMachine.cpp:129

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

Definition NVPTXTargetMachine.cpp:222

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

Definition NVPTXTargetMachine.cpp:218

This class provides access to building LLVM's passes.

LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same_v< PassT, PassManager > > addPass(PassT &&Pass)

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

StringRef - Represent a constant reference to a string, i.e.

void setRequiresStructuredCFG(bool Value)

std::unique_ptr< const MCSubtargetInfo > STI

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

LLVM Value Representation.

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

Interfaces for registering analysis passes, producing common pass manager configurations,...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ ADDRESS_SPACE_SHARED_CLUSTER

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

void initializeNVPTXLowerAllocaPass(PassRegistry &)

LLVM_ABI char & EarlyMachineLICMID

This pass performs loop invariant code motion on machine instructions.

FunctionPass * createNVPTXIRPeepholePass()

ModulePass * createNVPTXAssignValidGlobalNamesPass()

void initializeNVPTXPrologEpilogPassPass(PassRegistry &)

MachineFunctionPass * createNVPTXReplaceImageHandlesPass()

FunctionPass * createNVPTXLowerUnreachablePass(bool TrapUnreachable, bool NoTrapAfterNoreturn)

void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &)

ModulePass * createExpandVariadicsPass(ExpandVariadicsMode)

LLVM_ABI char & RegisterCoalescerID

RegisterCoalescer - This pass merges live ranges to eliminate copies.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)

A function to deduce a function pass type and wrap it in the templated adaptor.

ModulePass * createGenericToNVVMLegacyPass()

void initializeNVPTXLowerAggrCopiesPass(PassRegistry &)

void initializeNVPTXExternalAAWrapperPass(PassRegistry &)

MachineFunctionPass * createNVPTXPrologEpilogPass()

MachineFunctionPass * createNVPTXProxyRegErasurePass()

LLVM_ABI char & TailDuplicateLegacyID

TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.

LLVM_ABI Pass * createLoadStoreVectorizerPass()

Create a legacy pass manager instance of the LoadStoreVectorizer pass.

LLVM_ABI FunctionPass * createNaryReassociatePass()

LLVM_ABI char & PatchableFunctionID

This pass implements the "patchable-function" attribute.

ImmutablePass * createNVPTXExternalAAWrapperPass()

void initializeNVPTXLowerArgsLegacyPassPass(PassRegistry &)

LLVM_ABI char & PostRASchedulerID

PostRAScheduler - This pass performs post register allocation scheduling.

LLVM_ABI char & RemoveLoadsIntoFakeUsesID

RemoveLoadsIntoFakeUses pass.

MachineFunctionPass * createNVPTXPeephole()

LLVM_ABI char & MachineSchedulerID

MachineScheduler - This pass schedules machine instructions.

LLVM_ABI char & PeepholeOptimizerLegacyID

PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...

FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOptLevel OptLevel)

createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG,...

LLVM_ABI char & PrologEpilogCodeInserterID

PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...

void initializeGenericToNVVMLegacyPassPass(PassRegistry &)

void initializeNVPTXPeepholePass(PassRegistry &)

void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &)

void initializeNVPTXLowerUnreachablePass(PassRegistry &)

FunctionPass * createNVPTXTagInvariantLoadsPass()

LLVM_ABI char & MachineLoopInfoID

MachineLoopInfo - This pass is a loop analysis pass.

void initializeNVVMReflectLegacyPassPass(PassRegistry &)

FunctionPass * createNVPTXLowerArgsPass()

CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)

Helper method for getting the code model, returning Default if CM does not have a value.

LLVM_ABI char & ShrinkWrapID

ShrinkWrap pass. Look for the best place to insert save and restore.

LLVM_ABI char & MachineLateInstrsCleanupID

MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...

void initializeNVPTXAAWrapperPassPass(PassRegistry &)

FunctionPass * createNVPTXImageOptimizerPass()

FunctionPass * createNVPTXLowerAllocaPass()

void initializeNVPTXIRPeepholePass(PassRegistry &)

MachineFunctionPass * createNVPTXForwardParamsPass()

PassManager< Module > ModulePassManager

Convenience typedef for a pass manager over modules.

LLVM_ABI char & OptimizePHIsLegacyID

OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...

LLVM_ABI FunctionPass * createSpeculativeExecutionPass()

LLVM_ABI char & StackMapLivenessID

StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...

LLVM_ABI char & FuncletLayoutID

This pass lays out funclets contiguously.

FunctionPass * createAllocaHoisting()

void initializeNVVMIntrRangePass(PassRegistry &)

LLVM_ABI char & PostRAMachineSinkingID

This pass perform post-ra machine sink for COPY instructions.

CodeGenOptLevel

Code generation optimization level.

LLVM_ABI char & StackSlotColoringID

StackSlotColoring - This pass performs stack slot coloring.

void initializeNVPTXAsmPrinterPass(PassRegistry &)

LLVM_ABI FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)

FunctionPass * createLowerAggrCopies()

LLVM_ABI char & ProcessImplicitDefsID

ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.

void initializeNVPTXTagInvariantLoadLegacyPassPass(PassRegistry &)

LLVM_ABI FunctionPass * createGVNPass()

Create a legacy GVN pass.

FunctionPass * createNVPTXAtomicLowerPass()

ModulePass * createNVPTXCtorDtorLoweringLegacyPass()

LLVM_ABI char & MachineCSELegacyID

MachineCSE - This pass performs global CSE on machine instructions.

PassManager< Function > FunctionPassManager

Convenience typedef for a pass manager over functions.

LLVM_ABI char & LiveVariablesID

LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...

LLVM_ABI char & EarlyTailDuplicateLegacyID

Duplicate blocks with unconditional branches into tails of their predecessors.

void initializeNVPTXAllocaHoistingPass(PassRegistry &)

Target & getTheNVPTXTarget64()

LLVM_ABI char & StackColoringLegacyID

StackSlotColoring - This pass performs stack coloring and merging.

LLVM_ABI FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)

void initializeNVPTXProxyRegErasurePass(PassRegistry &)

ImmutablePass * createNVPTXAAWrapperPass()

LLVM_ABI char & MachineSinkingLegacyID

MachineSinking - This pass performs sinking on machine instructions.

ModulePass * createNVVMReflectPass(unsigned int SmVersion)

LLVM_ABI char & TwoAddressInstructionPassID

TwoAddressInstruction - This pass reduces two-address instructions to use two operands.

LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

LLVM_ABI char & LocalStackSlotAllocationID

LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...

LLVM_ABI FunctionPass * createStraightLineStrengthReducePass()

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

LLVM_ABI FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)

LLVM_ABI char & PHIEliminationID

PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.

LLVM_ABI llvm:🆑:opt< bool > NoKernelInfoEndLTO

LLVM_ABI FunctionPass * createSROAPass(bool PreserveCFG=true)

void initializeNVPTXAtomicLowerPass(PassRegistry &)

void initializeNVPTXForwardParamsPassPass(PassRegistry &)

LLVM_ABI char & MachineCopyPropagationID

MachineCopyPropagation - This pass performs copy propagation on machine instructions.

LLVM_ABI char & DeadMachineInstructionElimID

DeadMachineInstructionElim - This pass removes dead machine instructions.

Target & getTheNVPTXTarget32()

void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &)

Implement std::hash so that hash_code can be used in STL containers.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)

Factory function: default behavior is to call new using the supplied allocator.

RegisterTargetMachine - Helper template for registering a target machine implementation,...