PHIElimination.cpp Source File (original) (raw)

44#include

45#include

46#include

48using namespace llvm;

50#define DEBUG_TYPE "phi-node-elimination"

55 cl::desc("Disable critical edge splitting "

56 "during PHI elimination"));

61 cl::desc("Split all critical edges during "

62 "PHI elimination"));

66 cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));

68namespace {

70class PHIEliminationImpl {

84 bool AllEdgesCritical);

100

103

104 using BBVRegPair = std::pair<unsigned, Register>;

106

107

108 VRegPHIUse VRegPHIUseCount;

109

110

112

113

114 using LoweredPHIMap =

116 LoweredPHIMap LoweredPHIs;

117

120

121public:

126 auto *MDTWrapper =

128 auto *PDTWrapper =

130 LV = LVWrapper ? &LVWrapper->getLV() : nullptr;

131 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;

132 MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;

133 MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr;

134 PDT = PDTWrapper ? &PDTWrapper->getPostDomTree() : nullptr;

135 }

136

138 : LV(AM.getCachedResult(MF)),

139 LIS(AM.getCachedResult(MF)),

140 MLI(AM.getCachedResult(MF)),

141 MDT(AM.getCachedResult(MF)),

142 PDT(AM.getCachedResult(MF)),

143 MFAM(&AM) {}

144

145 bool run(MachineFunction &MF);

146};

147

149public:

150 static char ID;

151

152 PHIElimination() : MachineFunctionPass(ID) {

154 }

155

156 bool runOnMachineFunction(MachineFunction &MF) override {

157 PHIEliminationImpl Impl(this);

158 return Impl.run(MF);

159 }

160

161 MachineFunctionProperties getSetProperties() const override {

162 return MachineFunctionProperties().setNoPHIs();

163 }

164

165 void getAnalysisUsage(AnalysisUsage &AU) const override;

166};

167

168}

169

173 PHIEliminationImpl Impl(MF, MFAM);

174 bool Changed = Impl.run(MF);

184 return PA;

185}

186

187 STATISTIC(NumLowered, "Number of phis lowered");

188 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");

189 STATISTIC(NumReused, "Number of reused lowered phis");

190

191char PHIElimination::ID = 0;

192

194

196 "Eliminate PHI nodes for register allocation", false,

197 false)

200 "Eliminate PHI nodes for register allocation", false, false)

201

202void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {

212}

213

216

218 MachineDomTreeUpdater::UpdateStrategy::Lazy);

219

221

222

224

225

226 std::vector<SparseBitVector<>> LiveInSets;

227 if (LV) {

228 LiveInSets.resize(MF.size());

229 for (unsigned Index = 0, e = MRI->getNumVirtRegs(); Index != e; ++Index) {

230

231

235 continue;

239 while (AliveBlockItr != EndItr) {

240 unsigned BlockNum = *(AliveBlockItr++);

241 LiveInSets[BlockNum].set(Index);

242 }

243

244

246 if (VI.Kills.size() > 1 ||

247 (.Kills.empty() && VI.Kills.front()->getParent() != DefMBB))

248 for (auto *MI : VI.Kills)

249 LiveInSets[MI->getParent()->getNumber()].set(Index);

250 }

251 }

252

253 for (auto &MBB : MF)

255 SplitPHIEdges(MF, MBB, MLI, (LV ? &LiveInSets : nullptr), MDTU);

256 }

257

258

259 MRI->leaveSSA();

260

261

262 if (LV || LIS)

263 analyzePHINodes(MF);

264

265

266 for (auto &MBB : MF)

267 Changed |= EliminatePHINodes(MF, MBB);

268

269

272 if (MRI->use_nodbg_empty(DefReg)) {

273 if (LIS)

276 }

277 }

278

279

280 for (auto &I : LoweredPHIs) {

281 if (LIS)

283 MF.deleteMachineInstr(I.first);

284 }

285

286 LoweredPHIs.clear();

287 ImpDefs.clear();

288 VRegPHIUseCount.clear();

289

290 MF.getProperties().setNoPHIs();

291

293}

294

295

296

297bool PHIEliminationImpl::EliminatePHINodes(MachineFunction &MF,

300 return false;

301

302

305

306

307

308

309

310 bool AllEdgesCritical = MBB.pred_size() >= 2;

312 if (Pred->succ_size() < 2) {

313 AllEdgesCritical = false;

314 break;

315 }

316 }

317

319 LowerPHINode(MBB, LastPHIIt, AllEdgesCritical);

320

321 return true;

322}

323

324

325

329 if (!DI.isImplicitDef())

330 return false;

331 return true;

332}

333

334

340 return false;

341 }

342 return true;

343}

344

347 bool AllEdgesCritical) {

348 ++NumLowered;

349

351

352

354

359

360

363 bool EliminateNow = true;

364 bool reusedIncoming = false;

365

366

367

368

372

373

375 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);

376 else {

377

378

379

380

382 if (AllEdgesCritical)

383 Entry = &LoweredPHIs[MPhi];

384 if (Entry && *Entry) {

385

386 IncomingReg = *Entry;

387 reusedIncoming = true;

388 ++NumReused;

390 << *MPhi);

391 } else {

394 if (Entry) {

395 EliminateNow = false;

396 *Entry = IncomingReg;

397 }

398 }

399

400

402 MBB, AfterPHIsIt, MPhi->getDebugLoc(), IncomingReg, DestReg);

403 }

404

406

412 (void)Res;

413 }

414

415

416 if (LV) {

417 if (IncomingReg) {

419

421 bool IsPHICopyAfterOldKill = false;

422

423 if (reusedIncoming && (OldKill = VI.findKill(&MBB))) {

424

425

426

427

428

430 ++I) {

431 if (I == PHICopy)

432 break;

433

434 if (I == OldKill) {

435 IsPHICopyAfterOldKill = true;

436 break;

437 }

438 }

439 }

440

441

442

443

444 if (IsPHICopyAfterOldKill) {

445 LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);

448 }

449

450

451

452

453

454

455 if (!OldKill || IsPHICopyAfterOldKill)

457 }

458

459

460

461

463

464

468 }

469 }

470

471

472 if (LIS) {

474

476 if (IncomingReg) {

477

478

481 if (!IncomingVNI)

482 IncomingVNI =

485 MBBStartIndex, DestCopyIndex.getRegSlot(), IncomingVNI));

486 }

487

489 assert(!DestLI.empty() && "PHIs should have non-empty LiveIntervals.");

490

492

494 for (auto &SR : DestLI.subranges())

496

497 for (auto LR : ToUpdate) {

498 auto DestSegment = LR->find(MBBStartIndex);

499 assert(DestSegment != LR->end() &&

500 "PHI destination must be live in block");

501

502 if (LR->endIndex().isDead()) {

503

504

505

506 VNInfo *OrigDestVNI = LR->getVNInfoAt(DestSegment->start);

507 assert(OrigDestVNI && "PHI destination should be live at block entry.");

508 LR->removeSegment(DestSegment->start, DestSegment->start.getDeadSlot());

510 LR->removeValNo(OrigDestVNI);

511 continue;

512 }

513

514

515

516

517 if (DestSegment->start > NewStart) {

518 VNInfo *VNI = LR->getVNInfoAt(DestSegment->start);

519 assert(VNI && "value should be defined for known segment");

520 LR->addSegment(

522 } else if (DestSegment->start < NewStart) {

523 assert(DestSegment->start >= MBBStartIndex);

525 LR->removeSegment(DestSegment->start, NewStart);

526 }

527 VNInfo *DestVNI = LR->getVNInfoAt(NewStart);

528 assert(DestVNI && "PHI destination should be live at its definition.");

529 DestVNI->def = NewStart;

530 }

531 }

532

533

534 if (LV || LIS) {

535 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {

537 --VRegPHIUseCount[BBVRegPair(

540 }

541 }

542 }

543

544

545

547 for (int i = NumSrcs - 1; i >= 0; --i) {

553 "Machine PHI Operands must all be virtual registers!");

554

555

556

558

559

560

561

562 if (!MBBsInsertedInto.insert(&opBlock).second)

563 continue;

564

569 "Expected operand 0 to be a reg def!");

570

571

573 "Expected a single use from UnspillableTerminator");

575

576

577 if (LV) {

582 }

583

584 continue;

585 }

586

587

588

591

592

594 if (!reusedIncoming && IncomingReg) {

595 if (SrcUndef) {

596

597

598

599 NewSrcInstr =

601 TII->get(TargetOpcode::IMPLICIT_DEF), IncomingReg);

602

603

606 ImpDefs.insert(DefMI);

607 } else {

608

609

611 SrcReg, SrcSubReg, IncomingReg);

612 }

613 }

614

615

616

617

618 if (LV && !SrcUndef &&

619 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&

620 !LV->isLiveOut(SrcReg, opBlock)) {

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

640 if (Term->readsRegister(SrcReg, nullptr))

641 KillInst = Term;

642 }

643

644 if (KillInst == opBlock.end()) {

645

646

647 if (reusedIncoming || !IncomingReg) {

648

649 KillInst = InsertPos;

650 while (KillInst != opBlock.begin()) {

651 --KillInst;

652 if (KillInst->isDebugInstr())

653 continue;

654 if (KillInst->readsRegister(SrcReg, nullptr))

655 break;

656 }

657 } else {

658

659 KillInst = NewSrcInstr;

660 }

661 }

662 assert(KillInst->readsRegister(SrcReg, nullptr) &&

663 "Cannot find kill instruction");

664

665

667

668

669 unsigned opBlockNum = opBlock.getNumber();

671 }

672

673 if (LIS) {

674 if (NewSrcInstr) {

677 }

678

679 if (!SrcUndef &&

680 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {

682

687

688

689 if (VNI && VNI->def != startIdx) {

691 break;

692 }

693 }

694

699 if (Term->readsRegister(SrcReg, nullptr))

700 KillInst = Term;

701 }

702

703 if (KillInst == opBlock.end()) {

704

705

706 if (reusedIncoming || !IncomingReg) {

707

708 KillInst = InsertPos;

709 while (KillInst != opBlock.begin()) {

710 --KillInst;

711 if (KillInst->isDebugInstr())

712 continue;

713 if (KillInst->readsRegister(SrcReg, nullptr))

714 break;

715 }

716 } else {

717

718 KillInst = std::prev(InsertPos);

719 }

720 }

721 assert(KillInst->readsRegister(SrcReg, nullptr) &&

722 "Cannot find kill instruction");

723

727 for (auto &SR : SrcLI.subranges()) {

728 SR.removeSegment(LastUseIndex.getRegSlot(),

730 }

731 }

732 }

733 }

734 }

735

736

737 if (EliminateNow) {

738 if (LIS)

740 MF.deleteMachineInstr(MPhi);

741 }

742}

743

744

745

746

747

748void PHIEliminationImpl::analyzePHINodes(const MachineFunction &MF) {

749 for (const auto &MBB : MF) {

750 for (const auto &BBI : MBB) {

751 if (!BBI.isPHI())

752 break;

753 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {

754 if (!BBI.getOperand(i).isUndef()) {

755 ++VRegPHIUseCount[BBVRegPair(

756 BBI.getOperand(i + 1).getMBB()->getNumber(),

757 BBI.getOperand(i).getReg())];

758 }

759 }

760 }

761 }

762}

763

764bool PHIEliminationImpl::SplitPHIEdges(

768 return false;

769

771 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();

772

775 BBI != BBE && BBI->isPHI(); ++BBI) {

776 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {

777 Register Reg = BBI->getOperand(i).getReg();

779

781 continue;

782

783

784

786 continue;

789 continue;

790

791

792

793

794

795

796

797 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);

799 continue;

800 if (ShouldSplit) {

804 }

805

806

807

808

809

810

811

812

813

814 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);

815

816

817 if (!ShouldSplit && CurLoop != PreLoop) {

819 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";

820 if (PreLoop)

821 dbgs() << "PreLoop: " << *PreLoop;

822 if (CurLoop)

823 dbgs() << "CurLoop: " << *CurLoop;

824 });

825

826

827

828

829 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);

830 }

832 continue;

835 LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");

836 continue;

837 }

839 ++NumCriticalEdgesSplit;

840 }

841 }

843}

844

846 assert((LV || LIS) &&

847 "isLiveIn() requires either LiveVariables or LiveIntervals");

848 if (LIS)

850 else

852}

853

854bool PHIEliminationImpl::isLiveOutPastPHIs(Register Reg,

856 assert((LV || LIS) &&

857 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");

858

859

860

861

862

863 if (LIS) {

867 return true;

868 return false;

869 } else {

871 }

872}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

This file defines the DenseMap class.

static bool allPhiOperandsUndefined(const MachineInstr &MPhi, const MachineRegisterInfo &MRI)

Return true if all sources of the phi node are implicit_def's, or undef's.

Definition PHIElimination.cpp:335

static cl::opt< bool > NoPhiElimLiveOutEarlyExit("no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden, cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."))

static bool isImplicitlyDefined(Register VirtReg, const MachineRegisterInfo &MRI)

Return true if all defs of VirtReg are implicit-defs.

Definition PHIElimination.cpp:326

static cl::opt< bool > DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), cl::Hidden, cl::desc("Disable critical edge splitting " "during PHI elimination"))

static cl::opt< bool > SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false), cl::Hidden, cl::desc("Split all critical edges during " "PHI elimination"))

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)

bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)

This file defines the SmallPtrSet class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

Represent the analysis usage information of a pass.

LiveInterval - This class represents the liveness of a register, or stack slot.

iterator_range< subrange_iterator > subranges()

SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const

Return the first index in the given basic block.

SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)

LiveInterval & getOrCreateEmptyInterval(Register Reg)

Return an existing interval for Reg.

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

void RemoveMachineInstrFromMaps(MachineInstr &MI)

VNInfo::Allocator & getVNInfoAllocator()

SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const

Return the last index in the given basic block.

LiveInterval & getInterval(Register Reg)

LLVM_ABI LiveInterval::Segment addSegmentToEndOfBlock(Register Reg, MachineInstr &startInst)

Given a register and an instruction, adds a live segment from that instruction to the end of its MBB.

bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const

LLVM_ABI iterator addSegment(Segment S)

Add the specified Segment to this range, merging segments as appropriate.

bool liveAt(SlotIndex index) const

VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)

getNextValue - Create a new value number and return it.

LLVM_ABI void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)

Remove the specified interval from this live range.

VNInfo * getVNInfoAt(SlotIndex Idx) const

getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.

bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI)

removeVirtualRegisterDead - Remove the specified kill of the virtual register from the live variable ...

bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI)

removeVirtualRegisterKilled - Remove the specified kill of the virtual register from the live variabl...

LLVM_ABI void removeVirtualRegistersKilled(MachineInstr &MI)

removeVirtualRegistersKilled - Remove all killed info for the specified instruction.

void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)

addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...

LLVM_ABI bool isLiveOut(Register Reg, const MachineBasicBlock &MBB)

isLiveOut - Determine if Reg is live out from MBB, when not considering PHI nodes.

bool isLiveIn(Register Reg, const MachineBasicBlock &MBB)

void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)

addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...

LLVM_ABI VarInfo & getVarInfo(Register Reg)

getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.

bool contains(const LoopT *L) const

Return true if the specified loop is contained within in this loop.

BlockT * getHeader() const

LoopT * getLoopFor(const BlockT *BB) const

Return the inner most loop that BB lives in.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

unsigned pred_size() const

bool isEHPad() const

Returns true if the block is a landing pad.

MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<> > *LiveInSets=nullptr, MachineDomTreeUpdater *MDTU=nullptr)

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

LLVM_ABI iterator SkipPHIsAndLabels(iterator I)

Return the first instruction in MBB after I that is not a PHI or a label.

MachineInstr * remove(MachineInstr *I)

Remove the unbundled instruction from the instruction list without deleting it.

unsigned succ_size() const

LLVM_ABI void dump() const

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

iterator_range< succ_iterator > successors()

iterator_range< pred_iterator > predecessors()

MachineInstrBundleIterator< MachineInstr > iterator

Analysis pass which computes a MachineDominatorTree.

DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Location of a PHI instruction that is also a debug-info variable value, for the duration of register ...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

DenseMap< unsigned, DebugPHIRegallocPos > DebugPHIPositions

Map of debug instruction numbers to the position of their PHI instructions during register allocation...

Representation of each machine instruction.

bool isImplicitDef() const

const MachineBasicBlock * getParent() const

unsigned getNumOperands() const

Retuns the total number of operands.

unsigned peekDebugInstrNum() const

Examine the instruction number of this MachineInstr.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

const MachineOperand & getOperand(unsigned i) const

Analysis pass that exposes the MachineLoopInfo for a machine function.

MachineOperand class - Representation of each machine instruction operand.

unsigned getSubReg() const

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineBasicBlock * getMBB() const

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

getReg - Returns the register number.

MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition PHIElimination.cpp:171

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

SlotIndex - An opaque wrapper around machine indexes.

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

SparseBitVectorIterator iterator

TargetInstrInfo - Interface to description of machine instruction set.

bool isUnspillableTerminator(const MachineInstr *MI) const

Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...

virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const

During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...

virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const

During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...

virtual const TargetInstrInfo * getInstrInfo() const

VNInfo - Value Number Information.

SlotIndex def

The index of the defining instruction.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

initializer< Ty > init(const Ty &Val)

PointerTypeMap run(const Module &M)

Compute the PointerTypeMap for the module M.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()

Returns the minimum set of Analyses that all machine function passes must preserve.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, Register SrcReg)

findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...

LLVM_ABI unsigned SplitAllCriticalEdges(Function &F, const CriticalEdgeSplittingOptions &Options=CriticalEdgeSplittingOptions())

Loop over all of the edges in the CFG, breaking critical edges as they are found.

LLVM_ABI void initializePHIEliminationPass(PassRegistry &)

LLVM_ABI char & PHIEliminationID

PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.

Definition PHIElimination.cpp:193

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

This represents a simple continuous liveness interval for a value.

VarInfo - This represents the regions where a virtual register is live in the program.

SparseBitVector AliveBlocks

AliveBlocks - Set of blocks in which this value is alive completely through.