LLVM: lib/Target/PowerPC/PPCCallingConv.cpp Source File (original) (raw)
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11using namespace llvm;
12
16 llvm_unreachable("The AnyReg calling convention is only supported by the " \
17 "stackmap and patchpoint intrinsics.");
18
19 return false;
20}
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26 MVT &LocVT,
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32 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
33 PPC::X7, PPC::X8, PPC::X9, PPC::X10};
34 const unsigned ELF64NumArgGPRs = std::size(ELF64ArgGPRs);
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36 unsigned FirstUnallocGPR = State.getFirstUnallocated(ELF64ArgGPRs);
37 if (FirstUnallocGPR == ELF64NumArgGPRs)
38 return false;
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40
41
42
43 if (LocVT == MVT::f32 || LocVT == MVT::f64)
44 State.AllocateReg(ELF64ArgGPRs);
45 else if (LocVT.is128BitVector() || (LocVT == MVT::f128)) {
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51 if ((State.AllocateReg(ELF64ArgGPRs) - PPC::X3) % 2 == 1)
52 State.AllocateReg(ELF64ArgGPRs);
53 State.AllocateReg(ELF64ArgGPRs);
54 }
55 return false;
56}
57
64
66 MVT &LocVT,
70 static const MCPhysReg ArgRegs[] = {
71 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
72 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
73 };
74 const unsigned NumArgRegs = std::size(ArgRegs);
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76 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
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82 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
83 State.AllocateReg(ArgRegs[RegNum]);
84 }
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89 return false;
90}
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95 static const MCPhysReg ArgRegs[] = {
96 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
97 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
98 };
99 const unsigned NumArgRegs = std::size(ArgRegs);
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101 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
102 int RegsLeft = NumArgRegs - RegNum;
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106 if (RegNum != NumArgRegs && RegsLeft < 4) {
107 for (int i = 0; i < RegsLeft; i++) {
108 State.AllocateReg(ArgRegs[RegNum + i]);
109 }
110 }
111
112 return false;
113}
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116 MVT &LocVT,
120 static const MCPhysReg ArgRegs[] = {
121 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
122 PPC::F8
123 };
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125 const unsigned NumArgRegs = std::size(ArgRegs);
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127 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
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131 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
132 State.AllocateReg(ArgRegs[RegNum]);
133 }
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139 return false;
140}
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144 MVT &LocVT,
148 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
149 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
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151
153 if ()
154 return false;
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156 unsigned i;
157 for (i = 0; i < std::size(HiRegList); ++i)
158 if (HiRegList[i] == Reg)
159 break;
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161 MCRegister T = State.AllocateReg(LoRegList[i]);
162 (void)T;
163 assert(T == LoRegList[i] && "Could not allocate register");
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167 LocVT, LocInfo));
168 return true;
169}
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173 MVT &LocVT,
177 static const MCPhysReg HiRegList[] = { PPC::R3 };
178 static const MCPhysReg LoRegList[] = { PPC::R4 };
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181 MCRegister Reg = State.AllocateReg(HiRegList, LoRegList);
182 if ()
183 return false;
184
185 unsigned i;
186 for (i = 0; i < std::size(HiRegList); ++i)
187 if (HiRegList[i] == Reg)
188 break;
189
192 LocVT, LocInfo));
193 return true;
194}
195
196#include "PPCGenCallingConv.inc"
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
bool CC_PPC64_ELF_Shadow_GPR_Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition PPCCallingConv.cpp:25
static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition PPCCallingConv.cpp:65
static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition PPCCallingConv.cpp:92
bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &, CCValAssign::LocInfo &, ISD::ArgFlagsTy &, CCState &)
Definition PPCCallingConv.cpp:13
static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition PPCCallingConv.cpp:172
static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition PPCCallingConv.cpp:143
static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition PPCCallingConv.cpp:115
static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition PPCCallingConv.cpp:58
CCState - This class holds information needed while lowering arguments and return values.
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP)
Wrapper class representing physical registers. Should be passed by value.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...