PPCMCCodeEmitter.cpp Source File (original) (raw)

27#include

28#include

30using namespace llvm;

32#define DEBUG_TYPE "mccodeemitter"

34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");

39}

45 const MCOperand &MO = MI.getOperand(OpNo);

55 return 0;

56}

61 unsigned Opcode = MI.getOpcode();

63 return false;

65 switch (Opcode) {

66 default:

67#ifndef NDEBUG

69#endif

70 return false;

71 case PPC::BL8_NOTOC:

72 case PPC::BL8_NOTOC_TLS:

73 case PPC::BL8_NOTOC_RM:

74 return true;

75#ifndef NDEBUG

76 case PPC::BL8:

77 case PPC::BL:

78 case PPC::BL8_TLS:

79 case PPC::BL_TLS:

80 case PPC::BLA8:

81 case PPC::BLA:

82 case PPC::BCCL:

83 case PPC::BCCLA:

84 case PPC::BCL:

85 case PPC::BCLn:

86 case PPC::BL8_NOP:

87 case PPC::BL_NOP:

88 case PPC::BL8_NOP_TLS:

89 case PPC::BLA8_NOP:

90 case PPC::BCTRL8:

91 case PPC::BCTRL:

92 case PPC::BCCCTRL8:

93 case PPC::BCCCTRL:

94 case PPC::BCCTRL8:

95 case PPC::BCCTRL:

96 case PPC::BCCTRL8n:

97 case PPC::BCCTRLn:

98 case PPC::BL8_RM:

99 case PPC::BLA8_RM:

100 case PPC::BL8_NOP_RM:

101 case PPC::BLA8_NOP_RM:

102 case PPC::BCTRL8_RM:

103 case PPC::BCTRL8_LDinto_toc:

104 case PPC::BCTRL8_LDinto_toc_RM:

105 case PPC::BL8_TLS_:

106 case PPC::TCRETURNdi8:

107 case PPC::TCRETURNai8:

108 case PPC::TCRETURNri8:

109 case PPC::TAILBCTR8:

110 case PPC::TAILB8:

111 case PPC::TAILBA8:

112 case PPC::BCLalways:

113 case PPC::BLRL:

114 case PPC::BCCLRL:

115 case PPC::BCLRL:

116 case PPC::BCLRLn:

117 case PPC::BDZL:

118 case PPC::BDNZL:

119 case PPC::BDZLA:

120 case PPC::BDNZLA:

121 case PPC::BDZLp:

122 case PPC::BDNZLp:

123 case PPC::BDZLAp:

124 case PPC::BDNZLAp:

125 case PPC::BDZLm:

126 case PPC::BDNZLm:

127 case PPC::BDZLAm:

128 case PPC::BDNZLAm:

129 case PPC::BDZLRL:

130 case PPC::BDNZLRL:

131 case PPC::BDZLRLp:

132 case PPC::BDNZLRLp:

133 case PPC::BDZLRLm:

134 case PPC::BDNZLRLm:

135 case PPC::BL_RM:

136 case PPC::BLA_RM:

137 case PPC::BL_NOP_RM:

138 case PPC::BCTRL_RM:

139 case PPC::TCRETURNdi:

140 case PPC::TCRETURNai:

141 case PPC::TCRETURNri:

142 case PPC::BCTRL_LWZinto_toc:

143 case PPC::BCTRL_LWZinto_toc_RM:

144 case PPC::TAILBCTR:

145 case PPC::TAILB:

146 case PPC::TAILBA:

147 return false;

148#endif

149 }

150}

151

155 const MCOperand &MO = MI.getOperand(OpNo);

157

158

161 return 0;

162}

163

168 const MCOperand &MO = MI.getOperand(OpNo);

170

171

174 return 0;

175}

176

181 const MCOperand &MO = MI.getOperand(OpNo);

183

184

187 return 0;

188}

189

190unsigned

194 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");

196 << 1;

197 return RegBits;

198}

199

203 const MCOperand &MO = MI.getOperand(OpNo);

205

206

209 return 0;

210}

211

216 const MCOperand &MO = MI.getOperand(OpNo);

217 assert(!MO.isReg() && "Not expecting a register for this operand.");

220

221

223 return 0;

224}

225

232}

233

240}

241

245 const MCOperand &MO = MI.getOperand(OpNo);

248

249

252 return 0;

253}

254

255unsigned

259 const MCOperand &MO = MI.getOperand(OpNo);

262

263

266 return 0;

267}

268

269unsigned

273 const MCOperand &MO = MI.getOperand(OpNo);

274 if (MO.isImm()) {

276 "Expecting an immediate that is a multiple of 16");

278 }

279

280

283 return 0;

284}

285

286unsigned

290

291

292 const MCOperand &MO = MI.getOperand(OpNo);

293

294 assert(MO.isImm() && "Expecting an immediate operand.");

295 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");

296

297 unsigned DX = (MO.getImm() >> 3) & 0x3F;

298 return DX;

299}

300

305

306

307

308

309

310

311

312

313

314

315 const MCOperand &MO = MI.getOperand(OpNo);

318

319

320

321

323 switch (Expr->getKind()) {

324 default:

325 llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");

327

328 const MCSymbolRefExpr *SRE = cast(Expr);

329 (void)SRE;

330

336 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "

337 "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "

338 "VK_PPC_GOT_TPREL_PCREL.");

339

340 Fixups.push_back(

343

344

345 return 0;

346 }

348

349 const MCBinaryExpr *BE = cast(Expr);

351 "Binary expression opcode must be an add.");

352

355

356

359

362 llvm_unreachable("Expecting to have one constant and one relocation.");

363

365 (void)SRE;

366 assert(isInt<34>(cast(RHS)->getValue()) &&

367 "Value must fit in 34 bits.");

368

369

372 "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");

373

374 Fixups.push_back(

377

378

379 return 0;

380 }

381 }

382}

383

388

389 const MCOperand &MO = MI.getOperand(OpNo);

391}

392

393unsigned

397

398 const MCOperand &MO = MI.getOperand(OpNo);

401}

402

403unsigned

407

408 const MCOperand &MO = MI.getOperand(OpNo);

411}

412

413unsigned

417

418 const MCOperand &MO = MI.getOperand(OpNo);

421}

422

426 const MCOperand &MO = MI.getOperand(OpNo);

428

429

430

431

432

434 const MCSymbolRefExpr *SRE = cast(Expr);

439 bool isPPC64 = TT.isPPC64();

441}

442

446

447

448

449 const MCOperand &MO = MI.getOperand(OpNo+1);

453}

454

459 const MCOperand &MO = MI.getOperand(OpNo);

460 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||

461 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&

462 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));

464}

465

466

467

468

469

471 for (unsigned i = 0; i < MI.getNumOperands(); i++) {

473 if (&Op == &MO)

474 return i;

475 }

476 llvm_unreachable("This operand is not part of this instruction");

477 return ~0U;

478}

479

484 if (MO.isReg()) {

485

486

487 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&

488 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||

489 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);

491 unsigned Reg =

494 }

495

497 "Relocation required in an instruction that we cannot encode!");

499}

500

506

507

511 switch (Size) {

512 case 0:

513 break;

514 case 4:

515 support::endian::write<uint32_t>(CB, Bits, E);

516 break;

517 case 8:

518

519

520 support::endian::write<uint32_t>(CB, Bits >> 32, E);

521 support::endian::write<uint32_t>(CB, Bits, E);

522 break;

523 default:

525 }

526

527 ++MCNumEmitted;

528}

529

530

532 unsigned Opcode = MI.getOpcode();

534 return Desc.getSize();

535}

536

539}

540

541#include "PPCGenMCCodeEmitter.inc"

static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO)

PowerPC TLS Dynamic Call Fixup

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

This class represents an Operation in the Expression.

Binary assembler expressions.

const MCExpr * getLHS() const

Get the left-hand side expression of the binary operator.

const MCExpr * getRHS() const

Get the right-hand side expression of the binary operator.

Opcode getOpcode() const

Get the kind of this binary expression.

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

const MCRegisterInfo * getRegisterInfo() const

Base class for the full range of assembler expressions which are needed for parsing.

@ Constant

Constant expressions.

@ SymbolRef

References to labels and assigned expressions.

@ Binary

Binary expressions.

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

bool isCall() const

Return true if the instruction is a call.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Instances of this class represent operands of the MCInst class.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

uint16_t getEncodingValue(MCRegister Reg) const

Returns the encoding for Reg.

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

Represent a reference to a symbol from inside an expression.

VariantKind getKind() const

unsigned getDispSPE2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getDispRIHashEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getDispRI34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getDispRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getDispSPE8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override

Encode the given Inst to bytes and append to CB.

unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

bool isNoTOCCallInstr(const MCInst &MI) const

Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.

unsigned getDispRIX16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

bool isPrefixedInstruction(const MCInst &MI) const

unsigned getDispSPE4Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getMachineOpValue - Return binary encoding of operand.

unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, MCFixupKind Fixup) const

unsigned getInstSizeInBytes(const MCInst &MI) const

unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Triple - Helper class for working with autoconf configuration names.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Prefixed

This instruction is prefixed.

@ fixup_ppc_brcond14abs

14-bit absolute relocation for conditional branches.

@ fixup_ppc_half16

A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.

@ fixup_ppc_brcond14

14-bit PC relative relocation for conditional branches.

@ fixup_ppc_half16dq

A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.

@ fixup_ppc_half16ds

A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.

@ fixup_ppc_nofixup

Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...

@ fixup_ppc_br24abs

24-bit absolute relocation for direct branches like 'ba' and 'bla'.

unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)

getRegNumForOperand - some operands use different numbering schemes for the same registers.

This is an optimization pass for GlobalISel generic memory operations.

MCFixupKind

Extensible enumeration to represent the type of a fixup.

MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

Description of the encoding of one expression Op.