PPCMCTargetDesc.h File Reference (original) (raw)

#include "[llvm/MC/MCRegisterInfo.h](MCRegisterInfo%5F8h%5Fsource.html)"
#include "[llvm/Support/MathExtras.h](MathExtras%5F8h%5Fsource.html)"
#include <cstdint>
#include <memory>
#include "PPCGenRegisterInfo.inc"
#include "PPCGenInstrInfo.inc"
#include "PPCGenSubtargetInfo.inc"

Go to the source code of this file.

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::PPC
	Define some predicates that are used for node matching.
namespace	llvm::PPCII
	PPCII - This namespace holds all of the PowerPC target-specific per-instruction flags.

Macros
#define	GET_REGINFO_ENUM
#define	GET_INSTRINFO_ENUM
#define	GET_INSTRINFO_SCHED_ENUM
#define	GET_INSTRINFO_MC_HELPER_DECLS
#define	GET_SUBTARGETINFO_ENUM
#define	PPC_REGS0_7(X)
#define	PPC_REGS0_31(X)
#define	PPC_REGS_EVEN0_30(X)
#define	PPC_REGS0_63(X)
#define	PPC_REGS_NO0_31(Z, X)
#define	PPC_REGS_LO_HI(LO, HI)
#define	PPC_REGS0_7(X)
#define	PPC_REGS0_3(X)
#define	DEFINE_PPC_REGCLASSES

Typedefs
using	MCPhysReg
	An unsigned integer type large enough to represent all physical registers, but not necessarily virtual registers.

Enumerations
enum	{ llvm::PPCII::PPC970_First = 0x1 , llvm::PPCII::PPC970_Single = 0x2 , llvm::PPCII::PPC970_Cracked = 0x4 , llvm::PPCII::PPC970_Shift = 3 , llvm::PPCII::PPC970_Mask = 0x07 << PPC970_Shift }
enum	llvm::PPCII::PPC970_Unit { llvm::PPCII::PPC970_Pseudo = 0 << PPC970_Shift , llvm::PPCII::PPC970_FXU = 1 << PPC970_Shift , llvm::PPCII::PPC970_LSU = 2 << PPC970_Shift , llvm::PPCII::PPC970_FPU = 3 << PPC970_Shift , llvm::PPCII::PPC970_CRU = 4 << PPC970_Shift , llvm::PPCII::PPC970_VALU = 5 << PPC970_Shift , llvm::PPCII::PPC970_VPERM = 6 << PPC970_Shift , llvm::PPCII::PPC970_BRU = 7 << PPC970_Shift }
enum	{ llvm::PPCII::NewDef_Shift = 6 , llvm::PPCII::XFormMemOp = 0x1 << NewDef_Shift , llvm::PPCII::Prefixed = 0x1 << (NewDef_Shift + 1) , llvm::PPCII::SExt32To64 = 0x1 << (NewDef_Shift + 2) , llvm::PPCII::ZExt32To64 = 0x1 << (NewDef_Shift + 3) , llvm::PPCII::MemriOp = 0x1 << (NewDef_Shift + 4) }

Functions
const char *	llvm::PPC::stripRegisterPrefix (const char *RegName)
	stripRegisterPrefix - This method strips the character prefix from a register name so that only the number is left.
MCRegister	llvm::PPC::getRegNumForOperand (const MCInstrDesc &Desc, MCRegister Reg, unsigned OpNo)
	getRegNumForOperand - some operands use different numbering schemes for the same registers.
MCCodeEmitter *	llvm::createPPCMCCodeEmitter (const MCInstrInfo &MCII, MCContext &Ctx)
MCAsmBackend *	llvm::createPPCAsmBackend (const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter >	llvm::createPPCELFObjectWriter (bool Is64Bit, uint8_t OSABI)
	Construct an PPC ELF object writer.
std::unique_ptr< MCObjectTargetWriter >	llvm::createPPCMachObjectWriter (bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
	Construct a PPC Mach-O object writer.
std::unique_ptr< MCObjectTargetWriter >	llvm::createPPCXCOFFObjectWriter (bool Is64Bit)
	Construct a PPC XCOFF object writer.
static bool	llvm::isRunOfOnes (unsigned Val, unsigned &MB, unsigned &ME)
	Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side.
static bool	llvm::isRunOfOnes64 (uint64_t Val, unsigned &MB, unsigned &ME)
static bool	llvm::PPC::isVFRegister (MCRegister Reg)
static bool	llvm::PPC::isVRRegister (MCRegister Reg)
static bool	llvm::PPC::isDMRROWpRegister (unsigned Reg)

◆ DEFINE_PPC_REGCLASSES

#define DEFINE_PPC_REGCLASSES

Value:

static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \

static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \

static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \

static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \

static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \

static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \

static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \

static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \

static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \

static const MCPhysReg XRegsNoX0[32] = PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \

static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC::VSL, PPC::V); \

static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \

static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF); \

static const MCPhysReg CRBITRegs[32] = { \

PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, \

PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \

PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, \

PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \

PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, \

PPC::CR7EQ, PPC::CR7UN}; \

static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \

static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \

static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \

static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \

static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \

static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \

static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \

static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp);

#define PPC_REGS_EVEN0_30(X)

#define PPC_REGS_NO0_31(Z, X)

#define PPC_REGS_LO_HI(LO, HI)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

Definition at line 258 of file PPCMCTargetDesc.h.

◆ GET_INSTRINFO_ENUM

#define GET_INSTRINFO_ENUM

◆ GET_INSTRINFO_MC_HELPER_DECLS

#define GET_INSTRINFO_MC_HELPER_DECLS

◆ GET_INSTRINFO_SCHED_ENUM

#define GET_INSTRINFO_SCHED_ENUM

◆ GET_REGINFO_ENUM

◆ GET_SUBTARGETINFO_ENUM

#define GET_SUBTARGETINFO_ENUM

◆ PPC_REGS0_3

Value:

{ \

X##0, X##1, X##2, X##3 \

}

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

Definition at line 251 of file PPCMCTargetDesc.h.

◆ PPC_REGS0_31

#define PPC_REGS0_31	(	X	)

Value:

{ \

X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \

X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \

X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \

}

Definition at line 203 of file PPCMCTargetDesc.h.

◆ PPC_REGS0_63

#define PPC_REGS0_63	(	X	)

Value:

{ \

X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \

X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \

X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \

X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \

X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \

X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \

X##62, X##63 \

}

Definition at line 216 of file PPCMCTargetDesc.h.

◆ PPC_REGS0_7 [1/2]

◆ PPC_REGS0_7 [2/2]

◆ PPC_REGS_EVEN0_30

#define PPC_REGS_EVEN0_30	(	X	)

Value:

{ \

X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, X##16, X##18, X##20, \

X##22, X##24, X##26, X##28, X##30 \

}

Definition at line 210 of file PPCMCTargetDesc.h.

◆ PPC_REGS_LO_HI

#define PPC_REGS_LO_HI	(	LO,
HI )

Value:

{ \

LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \

LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \

LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \

LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \

HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \

HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \

HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \

HI##28, HI##29, HI##30, HI##31 \

}

Definition at line 234 of file PPCMCTargetDesc.h.

◆ PPC_REGS_NO0_31

#define PPC_REGS_NO0_31	(	Z,
X )

Value:

{ \

Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \

X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \

X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \

}

Definition at line 227 of file PPCMCTargetDesc.h.

◆ MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtual registers.

Definition at line 21 of file MCRegister.h.