PPCMachineScheduler.cpp Source File (original) (raw)

12using namespace llvm;

16 cl::desc("Disable scheduling addi instruction before"

20 cl::desc("Enable scheduling addi instruction as early"

21 "as possible post ra"),

27}

29bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,

30 SchedCandidate &TryCand,

33 return false;

35 SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;

36 SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;

37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {

38 TryCand.Reason = Stall;

39 return true;

40 }

41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {

42 TryCand.Reason = NoCand;

43 return true;

44 }

46 return false;

47}

57 return true;

58 }

82 bool SameBoundary = Zone != nullptr;

83 if (SameBoundary) {

95 }

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103 const SUnit *CandNextClusterSU =

105 const SUnit *TryCandNextClusterSU =

107 if (tryGreater(TryCand.SU == TryCandNextClusterSU,

108 Cand.SU == CandNextClusterSU, TryCand, Cand, Cluster))

110

111 if (SameBoundary) {

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124 if (SameBoundary) {

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153 return true;

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157 if (SameBoundary) {

158 if (biasAddiLoadCandidate(Cand, TryCand, *Zone))

160 }

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163}

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168 return false;

169

172 return true;

173 }

174 return false;

175}

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184 return true;

185 }

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static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand)

static cl::opt< bool > EnableAddiHeuristic("ppc-postra-bias-addi", cl::desc("Enable scheduling addi instruction as early" "as possible post ra"), cl::Hidden, cl::init(true))

static cl::opt< bool > DisableAddiLoadHeuristic("disable-ppc-sched-addi-load", cl::desc("Disable scheduling addi instruction before" "load for ppc"), cl::Hidden)

MachineSchedPolicy RegionPolicy

const TargetSchedModel * SchedModel

const TargetRegisterInfo * TRI

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

virtual void leaveMBB()

Tell the strategy that current MBB is done.

virtual void enterMBB(MachineBasicBlock *MBB)

Tell the strategy that MBB is about to be processed.

SUnit * pickNode(bool &IsTopNode) override

Pick the next node to schedule.

void enterMBB(MachineBasicBlock *MBB) override

Tell the strategy that MBB is about to be processed.

bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override

Apply a set of heuristics to a new candidate for PostRA scheduling.

bool biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) const

void leaveMBB() override

Tell the strategy that current MBB is done.

void initialize(ScheduleDAGMI *Dag) override

Initialize the strategy after building the DAG for a new region.

bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const override

Apply a set of heuristics to a new candidate.

void initialize(ScheduleDAGMI *Dag) override

Initialize the strategy after building the DAG for a new region.

SUnit * pickNode(bool &IsTopNode) override

Pick the next node to schedule.

Scheduling unit. This is a node in the scheduling DAG.

unsigned NodeNum

Entry # of node in the node vector.

MachineInstr * getInstr() const

Returns the representative MachineInstr for this SUnit.

Each Scheduling boundary is associated with ready queues.

unsigned getLatencyStallCycles(SUnit *SU)

Get the difference between the given SUnit's ready time and the current cycle.

unsigned getCurrMOps() const

Micro-ops issued in the current cycle.

bool isTrackingPressure() const

Return true if register pressure tracking is enabled.

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

const SUnit * getNextClusterPred() const

const SUnit * getNextClusterSucc() const

MachineFunction & MF

Machine function.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

unsigned getWeakLeft(const SUnit *SU, bool isTop)

bool tryPressure(const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)

bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)

bool tryGreater(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)

bool tryLess(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)

Return true if this heuristic determines order.

int biasPhysReg(const SUnit *SU, bool isTop)

Minimize physical register live ranges.

Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...

void initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel)

SchedResourceDelta ResDelta

unsigned DemandedResources

bool DisableLatencyHeuristic

PressureChange CriticalMax

PressureChange CurrentMax

bool IsAcyclicLatencyLimited