PPCReduceCRLogicals.cpp Source File (original) (raw)

26#include "llvm/Config/llvm-config.h"

29using namespace llvm;

31#define DEBUG_TYPE "ppc-reduce-cr-ops"

34 "Number of single-use binary CR logical ops contained in a block");

36 "Number of binary CR logical ops that can be used to split blocks");

37 STATISTIC(TotalCRLogicals, "Number of CR logical ops.");

39 "Number of nullary CR logical ops (CRSET/CRUNSET).");

40 STATISTIC(TotalUnaryCRLogicals, "Number of unary CR logical ops.");

41 STATISTIC(TotalBinaryCRLogicals, "Number of CR logical ops.");

43 "Number of blocks split on CR binary logical ops.");

45 "Number of blocks not split due to operands being identical.");

47 "Number of blocks not split due to operands being chained copies.");

49 "Number of blocks not split due to the wrong opcode.");

58 if (.isPHI())

59 continue;

62 for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {

64 if (MO.getMBB() == OrigMBB) {

66 if (MI.getOperand(i - 1).isReg()) {

68 if (DefMI->getParent() == NewMBB ||

71 break;

72 }

73 }

74 }

75 }

76 }

77}

89 "NewMBB must be a successor of OrigMBB");

91 if (.isPHI())

92 continue;

95 for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {

97 if (MO.getMBB() == OrigMBB) {

99 MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);

100 break;

101 }

102 }

103 }

104}

105

106namespace {

107struct BlockSplitInfo {

108 MachineInstr *OrigBranch;

109 MachineInstr *SplitBefore;

110 MachineInstr *SplitCond;

111 unsigned OrigSubreg;

112 unsigned SplitCondSubreg;

113 bool InvertNewBranch;

114 bool InvertOrigBranch;

115 bool BranchToFallThrough;

116 const MachineBranchProbabilityInfo *MBPI;

117 MachineInstr *MIToDelete;

118 MachineInstr *NewCond;

119 bool allInstrsInSameMBB() {

120 if (!OrigBranch || !SplitBefore || !SplitCond)

121 return false;

122 MachineBasicBlock *MBB = OrigBranch->getParent();

123 if (SplitBefore->getParent() != MBB || SplitCond->getParent() != MBB)

124 return false;

125 if (MIToDelete && MIToDelete->getParent() != MBB)

126 return false;

127 if (NewCond && NewCond->getParent() != MBB)

128 return false;

129 return true;

130 }

131};

132}

133

134

135

136

137

138

139

140

141

142

143static bool splitMBB(BlockSplitInfo &BSI) {

144 assert(BSI.allInstrsInSameMBB() &&

145 "All instructions must be in the same block.");

146

150 assert(MRI->isSSA() && "Can only do this while the function is in SSA form.");

153 dbgs() << "Don't know how to handle blocks that don't have exactly"

154 << " two successors.\n");

155 return false;

156 }

157

159 unsigned OrigBROpcode = BSI.OrigBranch->getOpcode();

160 unsigned InvertedOpcode =

161 OrigBROpcode == PPC::BC

162 ? PPC::BCn

163 : OrigBROpcode == PPC::BCn

164 ? PPC::BC

165 : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR;

166 unsigned NewBROpcode = BSI.InvertNewBranch ? InvertedOpcode : OrigBROpcode;

172 BSI.BranchToFallThrough ? OrigFallThrough : OrigTarget;

173

174

175

176

177

178

179

180

181

182

183 BranchProbability ProbToNewTarget, ProbFallThrough;

184 BranchProbability ProbOrigTarget, ProbOrigFallThrough;

187 if (BSI.MBPI) {

188 if (BSI.BranchToFallThrough) {

189 ProbToNewTarget = BSI.MBPI->getEdgeProbability(ThisMBB, OrigFallThrough) / 2;

190 ProbFallThrough = ProbToNewTarget.getCompl();

191 ProbOrigFallThrough = ProbToNewTarget / ProbToNewTarget.getCompl();

192 ProbOrigTarget = ProbOrigFallThrough.getCompl();

193 } else {

194 ProbToNewTarget = BSI.MBPI->getEdgeProbability(ThisMBB, OrigTarget) / 2;

195 ProbFallThrough = ProbToNewTarget.getCompl();

196 ProbOrigTarget = ProbToNewTarget / ProbToNewTarget.getCompl();

197 ProbOrigFallThrough = ProbOrigTarget.getCompl();

198 }

199 }

200

201

206 MF->insert(++It, NewMBB);

207

208

209 NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end());

211 if (!ProbOrigTarget.isUnknown()) {

216 }

217

218

219 ThisMBB->addSuccessor(NewBRTarget, ProbToNewTarget);

220 ThisMBB->addSuccessor(NewMBB, ProbFallThrough);

221

222

224 TII->get(NewBROpcode))

226 .addMBB(NewBRTarget);

228 TII->get(PPC::B))

230 if (BSI.MIToDelete)

232

233

235 if (BSI.NewCond) {

236 assert(FirstTerminator->getOperand(0).isReg() &&

237 "Can't update condition of unconditional branch.");

238 FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());

239 FirstTerminator->getOperand(0).setSubReg(BSI.OrigSubreg);

240 }

241 if (BSI.InvertOrigBranch)

242 FirstTerminator->setDesc(TII->get(InvertedOpcode));

243

244

245

246 for (auto *Succ : NewMBB->successors()) {

248 }

250

251

252

254

255 LLVM_DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump());

258 return true;

259}

260

262 return MI.getNumOperands() == 3;

263}

264

266 return MI.getNumOperands() == 1;

267}

268

269

270

271

272

273

274static void

276 bool &InvertNewBranch, bool &InvertOrigBranch,

277 bool &TargetIsFallThrough) {

278

279

280

281

282 if (BROp == PPC::BC || BROp == PPC::BCLR) {

283

284 switch (CROp) {

285 default:

286 llvm_unreachable("Don't know how to handle this CR logical.");

287 case PPC::CROR:

288 InvertNewBranch = false;

289 InvertOrigBranch = false;

290 TargetIsFallThrough = false;

291 return;

292 case PPC::CRAND:

293 InvertNewBranch = true;

294 InvertOrigBranch = false;

295 TargetIsFallThrough = true;

296 return;

297 case PPC::CRNAND:

298 InvertNewBranch = true;

299 InvertOrigBranch = true;

300 TargetIsFallThrough = false;

301 return;

302 case PPC::CRNOR:

303 InvertNewBranch = false;

304 InvertOrigBranch = true;

305 TargetIsFallThrough = true;

306 return;

307 case PPC::CRORC:

308 InvertNewBranch = UsingDef1;

309 InvertOrigBranch = !UsingDef1;

310 TargetIsFallThrough = false;

311 return;

312 case PPC::CRANDC:

313 InvertNewBranch = !UsingDef1;

314 InvertOrigBranch = !UsingDef1;

315 TargetIsFallThrough = true;

316 return;

317 }

318 } else if (BROp == PPC::BCn || BROp == PPC::BCLRn) {

319

320 switch (CROp) {

321 default:

322 llvm_unreachable("Don't know how to handle this CR logical.");

323 case PPC::CROR:

324 InvertNewBranch = true;

325 InvertOrigBranch = false;

326 TargetIsFallThrough = true;

327 return;

328 case PPC::CRAND:

329 InvertNewBranch = false;

330 InvertOrigBranch = false;

331 TargetIsFallThrough = false;

332 return;

333 case PPC::CRNAND:

334 InvertNewBranch = false;

335 InvertOrigBranch = true;

336 TargetIsFallThrough = true;

337 return;

338 case PPC::CRNOR:

339 InvertNewBranch = true;

340 InvertOrigBranch = true;

341 TargetIsFallThrough = false;

342 return;

343 case PPC::CRORC:

344 InvertNewBranch = !UsingDef1;

345 InvertOrigBranch = !UsingDef1;

346 TargetIsFallThrough = true;

347 return;

348 case PPC::CRANDC:

349 InvertNewBranch = UsingDef1;

350 InvertOrigBranch = !UsingDef1;

351 TargetIsFallThrough = false;

352 return;

353 }

354 } else

356}

357

358namespace {

359

361public:

362 static char ID;

363 struct CRLogicalOpInfo {

364 MachineInstr *MI;

365

366 std::pair<MachineInstr*, MachineInstr*> CopyDefs;

367 std::pair<MachineInstr*, MachineInstr*> TrueDefs;

368 unsigned IsBinary : 1;

369 unsigned IsNullary : 1;

370 unsigned ContainedInBlock : 1;

371 unsigned FeedsISEL : 1;

372 unsigned FeedsBR : 1;

373 unsigned FeedsLogical : 1;

374 unsigned SingleUse : 1;

375 unsigned DefsSingleUse : 1;

376 unsigned SubregDef1;

377 unsigned SubregDef2;

378 CRLogicalOpInfo() : MI(nullptr), IsBinary(0), IsNullary(0),

379 ContainedInBlock(0), FeedsISEL(0), FeedsBR(0),

380 FeedsLogical(0), SingleUse(0), DefsSingleUse(1),

381 SubregDef1(0), SubregDef2(0) { }

383 };

384

385private:

386 const PPCInstrInfo *TII = nullptr;

387 MachineFunction *MF = nullptr;

388 MachineRegisterInfo *MRI = nullptr;

389 const MachineBranchProbabilityInfo *MBPI = nullptr;

390

391

393 void initialize(MachineFunction &MFParm);

394 void collectCRLogicals();

395 bool handleCROp(unsigned Idx);

396 bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);

397 static bool isCRLogical(MachineInstr &MI) {

398 unsigned Opc = MI.getOpcode();

399 return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||

400 Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CRNOT ||

401 Opc == PPC::CREQV || Opc == PPC::CRANDC || Opc == PPC::CRORC ||

402 Opc == PPC::CRSET || Opc == PPC::CRUNSET || Opc == PPC::CR6SET ||

403 Opc == PPC::CR6UNSET;

404 }

405 bool simplifyCode() {

407

408

409 for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)

410 Changed |= handleCROp(i);

412 }

413

414public:

415 PPCReduceCRLogicals() : MachineFunctionPass(ID) {}

416

417 MachineInstr *lookThroughCRCopy(unsigned Reg, unsigned &Subreg,

418 MachineInstr *&CpDef);

419 bool runOnMachineFunction(MachineFunction &MF) override {

420 if (skipFunction(MF.getFunction()))

421 return false;

422

423

424 const PPCSubtarget &STI = MF.getSubtarget();

425 if (!STI.useCRBits())

426 return false;

427

429 collectCRLogicals();

430 return simplifyCode();

431 }

432 CRLogicalOpInfo createCRLogicalOpInfo(MachineInstr &MI);

433 void getAnalysisUsage(AnalysisUsage &AU) const override {

434 AU.addRequired();

435 AU.addRequired();

437 }

438};

439}

440

441#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

442LLVM_DUMP_METHOD void PPCReduceCRLogicals::CRLogicalOpInfo::dump() {

443 dbgs() << "CRLogicalOpMI: ";

445 dbgs() << "IsBinary: " << IsBinary << ", FeedsISEL: " << FeedsISEL;

446 dbgs() << ", FeedsBR: " << FeedsBR << ", FeedsLogical: ";

447 dbgs() << FeedsLogical << ", SingleUse: " << SingleUse;

448 dbgs() << ", DefsSingleUse: " << DefsSingleUse;

449 dbgs() << ", SubregDef1: " << SubregDef1 << ", SubregDef2: ";

450 dbgs() << SubregDef2 << ", ContainedInBlock: " << ContainedInBlock;

451 if (!IsNullary) {

452 dbgs() << "\nDefs:\n";

453 TrueDefs.first->dump();

454 }

455 if (IsBinary)

456 TrueDefs.second->dump();

457 dbgs() << "\n";

458 if (CopyDefs.first) {

459 dbgs() << "CopyDef1: ";

460 CopyDefs.first->dump();

461 }

462 if (CopyDefs.second) {

463 dbgs() << "CopyDef2: ";

464 CopyDefs.second->dump();

465 }

466}

467#endif

468

469PPCReduceCRLogicals::CRLogicalOpInfo

470PPCReduceCRLogicals::createCRLogicalOpInfo(MachineInstr &MIParam) {

471 CRLogicalOpInfo Ret;

472 Ret.MI = &MIParam;

473

475 Ret.IsNullary = 1;

476 Ret.TrueDefs = std::make_pair(nullptr, nullptr);

477 Ret.CopyDefs = std::make_pair(nullptr, nullptr);

478 } else {

479 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(),

480 Ret.SubregDef1, Ret.CopyDefs.first);

482 assert(Def1 && "Must be able to find a definition of operand 1.");

483 Ret.DefsSingleUse &=

485 Ret.DefsSingleUse &=

486 MRI->hasOneNonDBGUse(Ret.CopyDefs.first->getOperand(0).getReg());

488 Ret.IsBinary = 1;

489 MachineInstr *Def2 = lookThroughCRCopy(MIParam.getOperand(2).getReg(),

490 Ret.SubregDef2,

491 Ret.CopyDefs.second);

493 assert(Def2 && "Must be able to find a definition of operand 2.");

494 Ret.DefsSingleUse &=

496 Ret.DefsSingleUse &=

497 MRI->hasOneNonDBGUse(Ret.CopyDefs.second->getOperand(0).getReg());

498 Ret.TrueDefs = std::make_pair(Def1, Def2);

499 } else {

500 Ret.TrueDefs = std::make_pair(Def1, nullptr);

501 Ret.CopyDefs.second = nullptr;

502 }

503 }

504

505 Ret.ContainedInBlock = 1;

506

507 for (MachineInstr &UseMI :

509 unsigned Opc = UseMI.getOpcode();

510 if (Opc == PPC::ISEL || Opc == PPC::ISEL8)

511 Ret.FeedsISEL = 1;

512 if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR ||

513 Opc == PPC::BCLRn)

514 Ret.FeedsBR = 1;

515 Ret.FeedsLogical = isCRLogical(UseMI);

517 Ret.ContainedInBlock = 0;

518 }

519 Ret.SingleUse = MRI->hasOneNonDBGUse(MIParam.getOperand(0).getReg()) ? 1 : 0;

520

521

522 if (!Ret.IsNullary) {

523 Ret.ContainedInBlock &=

524 (MIParam.getParent() == Ret.TrueDefs.first->getParent());

525 if (Ret.IsBinary)

526 Ret.ContainedInBlock &=

527 (MIParam.getParent() == Ret.TrueDefs.second->getParent());

528 }

530 if (Ret.IsBinary && Ret.ContainedInBlock && Ret.SingleUse) {

531 NumContainedSingleUseBinOps++;

532 if (Ret.FeedsBR && Ret.DefsSingleUse)

533 NumToSplitBlocks++;

534 }

535 return Ret;

536}

537

538

539

540

541

542

543

544MachineInstr *PPCReduceCRLogicals::lookThroughCRCopy(unsigned Reg,

545 unsigned &Subreg,

546 MachineInstr *&CpDef) {

547 if (!Register::isVirtualRegister(Reg))

548 return nullptr;

549 MachineInstr *Copy = MRI->getVRegDef(Reg);

550 CpDef = Copy;

551 if ( Copy ->isCopy())

553 Register CopySrc = Copy->getOperand(1).getReg();

556

558 while (Me != B)

559 if ((--Me)->modifiesRegister(CopySrc, TRI))

560 return &*Me;

561 return nullptr;

562 }

563 return MRI->getVRegDef(CopySrc);

564}

565

566void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {

567 MF = &MFParam;

570 MBPI = &getAnalysis().getMBPI();

571

572 AllCRLogicalOps.clear();

573}

574

575

576

577

578

579

580bool PPCReduceCRLogicals::handleCROp(unsigned Idx) {

581

582

584 CRLogicalOpInfo CRI = AllCRLogicalOps[Idx];

585 if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&

586 CRI.DefsSingleUse) {

587 Changed = splitBlockOnBinaryCROp(CRI);

589 NumBlocksSplitOnBinaryCROp++;

590 }

592}

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) {

612 if (CRI.CopyDefs.first == CRI.CopyDefs.second) {

613 LLVM_DEBUG(dbgs() << "Unable to split as the two operands are the same\n");

614 NumNotSplitIdenticalOperands++;

615 return false;

616 }

617 if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() ||

618 CRI.TrueDefs.first->isPHI() || CRI.TrueDefs.second->isPHI()) {

620 dbgs() << "Unable to split because one of the operands is a PHI or "

621 "chain of copies.\n");

622 NumNotSplitChainCopies++;

623 return false;

624 }

625

626 if (CRI.MI->getOpcode() != PPC::CROR &&

627 CRI.MI->getOpcode() != PPC::CRAND &&

628 CRI.MI->getOpcode() != PPC::CRNOR &&

629 CRI.MI->getOpcode() != PPC::CRNAND &&

630 CRI.MI->getOpcode() != PPC::CRORC &&

631 CRI.MI->getOpcode() != PPC::CRANDC) {

632 LLVM_DEBUG(dbgs() << "Unable to split blocks on this opcode.\n");

633 NumNotSplitWrongOpcode++;

634 return false;

635 }

636 LLVM_DEBUG(dbgs() << "Splitting the following CR op:\n"; CRI.dump());

639

640 bool UsingDef1 = false;

641 MachineInstr *SplitBefore = &*Def2It;

642 for (auto E = CRI.MI->getParent()->end(); Def2It != E; ++Def2It) {

643 if (Def1It == Def2It) {

644 SplitBefore = &*Def1It;

645 UsingDef1 = true;

646 break;

647 }

648 }

649

650 LLVM_DEBUG(dbgs() << "We will split the following block:\n";);

651 LLVM_DEBUG(CRI.MI->getParent()->dump());

653

654

655 MachineInstr *Branch =

656 MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();

657

658

659

660

661

662 MachineBasicBlock *MBB = SplitBefore->getParent();

665 UsingDef1 ? CRI.TrueDefs.first : CRI.TrueDefs.second;

667 UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second;

668

669

670

671

672

673 MBB->splice(FirstTerminator, MBB, FirstInstrToMove);

674 if (FirstInstrToMove != SecondInstrToMove)

675 MBB->splice(FirstTerminator, MBB, SecondInstrToMove);

677

678 unsigned Opc = CRI.MI->getOpcode();

679 bool InvertOrigBranch, InvertNewBranch, TargetIsFallThrough;

681 InvertNewBranch, InvertOrigBranch,

682 TargetIsFallThrough);

683 MachineInstr *NewCond = CRI.CopyDefs.first;

684 MachineInstr *SplitCond = CRI.CopyDefs.second;

685 if (!UsingDef1) {

687 std::swap(CRI.SubregDef1, CRI.SubregDef2);

688 }

689 LLVM_DEBUG(dbgs() << "We will " << (InvertNewBranch ? "invert" : "copy"));

690 LLVM_DEBUG(dbgs() << " the original branch and the target is the "

691 << (TargetIsFallThrough ? "fallthrough block\n"

692 : "orig. target block\n"));

694 BlockSplitInfo BSI{

695 Branch, SplitBefore, SplitCond, CRI.SubregDef1,

696 CRI.SubregDef2, InvertNewBranch, InvertOrigBranch, TargetIsFallThrough,

697 MBPI, CRI.MI, NewCond};

699

700

702 bool Input1CRlogical =

703 CRI.TrueDefs.first && isCRLogical(*CRI.TrueDefs.first);

704 bool Input2CRlogical =

705 CRI.TrueDefs.second && isCRLogical(*CRI.TrueDefs.second);

706 if (Input1CRlogical)

707 AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.first));

708 if (Input2CRlogical)

709 AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.second));

710 }

712}

713

714void PPCReduceCRLogicals::collectCRLogicals() {

715 for (MachineBasicBlock &MBB : *MF) {

716 for (MachineInstr &MI : MBB) {

717 if (isCRLogical(MI)) {

718 AllCRLogicalOps.push_back(createCRLogicalOpInfo(MI));

719 TotalCRLogicals++;

720 if (AllCRLogicalOps.back().IsNullary)

721 TotalNullaryCRLogicals++;

722 else if (AllCRLogicalOps.back().IsBinary)

723 TotalBinaryCRLogicals++;

724 else

725 TotalUnaryCRLogicals++;

726 }

727 }

728 }

729}

730

732 "PowerPC Reduce CR logical Operation", false, false)

735 "PowerPC Reduce CR logical Operation", false, false)

736

737char PPCReduceCRLogicals::ID = 0;

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator MBBI

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Promote Memory to Register

static bool isBinary(MachineInstr &MI)

Definition PPCReduceCRLogicals.cpp:261

static bool isNullary(MachineInstr &MI)

Definition PPCReduceCRLogicals.cpp:265

static bool splitMBB(BlockSplitInfo &BSI)

Splits a MachineBasicBlock to branch before SplitBefore.

Definition PPCReduceCRLogicals.cpp:143

static void computeBranchTargetAndInversion(unsigned CROp, unsigned BROp, bool UsingDef1, bool &InvertNewBranch, bool &InvertOrigBranch, bool &TargetIsFallThrough)

Given a CR logical operation CROp, branch opcode BROp as well as a flag to indicate if the first oper...

Definition PPCReduceCRLogicals.cpp:275

static void addIncomingValuesToPHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB, MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI)

Given a basic block Successor that potentially contains PHIs, this function will look for PHIs that h...

Definition PPCReduceCRLogicals.cpp:84

static void updatePHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB, MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI)

Given a basic block Successor that potentially contains PHIs, this function will look for any incomin...

Definition PPCReduceCRLogicals.cpp:55

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, const llvm::StringTable &StandardNames, VectorLibrary VecLib)

Initialize the set of available library functions based on the specified target triple.

AnalysisUsage & addRequired()

LLVM Basic Block Representation.

static BranchProbability getUnknown()

BranchProbability getCompl() const

FunctionPass class - This class is used to implement most global optimizations.

LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)

Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...

void setCallFrameSize(unsigned N)

Set the call frame size on entry to this basic block.

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

LLVM_ABI void setSuccProbability(succ_iterator I, BranchProbability Prob)

Set successor probability of a given iterator.

succ_iterator succ_begin()

LLVM_ABI iterator getFirstTerminator()

Returns an iterator to the first terminator instruction of this basic block.

unsigned succ_size() const

LLVM_ABI void dump() const

LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

succ_reverse_iterator succ_rbegin()

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

iterator_range< succ_iterator > successors()

LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB is a successor of this block.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

BasicBlockListType::iterator iterator

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineInstr - Allocate a new MachineInstr.

void insert(iterator MBBI, MachineBasicBlock *MBB)

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

LLVM_ABI void dump() const

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

unsigned getSubReg() const

MachineBasicBlock * getMBB() const

void setMBB(MachineBasicBlock *MBB)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

void push_back(const T &Elt)

const TargetRegisterInfo & getRegisterInfo() const

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

auto find(R &&Range, const T &Val)

Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

FunctionPass * createPPCReduceCRLogicalsPass()

Definition PPCReduceCRLogicals.cpp:739

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.