PPCReduceCRLogicals.cpp Source File (original) (raw)

26#include "llvm/Config/llvm-config.h"

30using namespace llvm;

32#define DEBUG_TYPE "ppc-reduce-cr-ops"

35 "Number of single-use binary CR logical ops contained in a block");

37 "Number of binary CR logical ops that can be used to split blocks");

38 STATISTIC(TotalCRLogicals, "Number of CR logical ops.");

40 "Number of nullary CR logical ops (CRSET/CRUNSET).");

41 STATISTIC(TotalUnaryCRLogicals, "Number of unary CR logical ops.");

42 STATISTIC(TotalBinaryCRLogicals, "Number of CR logical ops.");

44 "Number of blocks split on CR binary logical ops.");

46 "Number of blocks not split due to operands being identical.");

48 "Number of blocks not split due to operands being chained copies.");

50 "Number of blocks not split due to the wrong opcode.");

59 if (.isPHI())

60 continue;

63 for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {

65 if (MO.getMBB() == OrigMBB) {

67 if (MI.getOperand(i - 1).isReg()) {

72 break;

73 }

74 }

75 }

76 }

77 }

78}

90 "NewMBB must be a successor of OrigMBB");

92 if (.isPHI())

93 continue;

96 for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {

98 if (MO.getMBB() == OrigMBB) {

100 MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);

101 break;

102 }

103 }

104 }

105}

106

119 return false;

122 return false;

124 return false;

126 return false;

127 return true;

128 }

129};

130

131

132

133

134

135

136

137

138

139

142 "All instructions must be in the same block.");

143

147 assert(MRI->isSSA() && "Can only do this while the function is in SSA form.");

150 dbgs() << "Don't know how to handle blocks that don't have exactly"

151 << " two successors.\n");

152 return false;

153 }

154

157 unsigned InvertedOpcode =

158 OrigBROpcode == PPC::BC

159 ? PPC::BCn

160 : OrigBROpcode == PPC::BCn

161 ? PPC::BC

162 : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR;

163 unsigned NewBROpcode = BSI.InvertNewBranch ? InvertedOpcode : OrigBROpcode;

170

171

172

173

174

175

176

177

178

179

180 BranchProbability ProbToNewTarget, ProbFallThrough;

181 BranchProbability ProbOrigTarget, ProbOrigFallThrough;

184 if (BSI.MBPI) {

187 ProbFallThrough = ProbToNewTarget.getCompl();

188 ProbOrigFallThrough = ProbToNewTarget / ProbToNewTarget.getCompl();

189 ProbOrigTarget = ProbOrigFallThrough.getCompl();

190 } else {

192 ProbFallThrough = ProbToNewTarget.getCompl();

193 ProbOrigTarget = ProbToNewTarget / ProbToNewTarget.getCompl();

194 ProbOrigFallThrough = ProbOrigTarget.getCompl();

195 }

196 }

197

198

203 MF->insert(++It, NewMBB);

204

205

206 NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end());

208 if (!ProbOrigTarget.isUnknown()) {

213 }

214

215

216 ThisMBB->addSuccessor(NewBRTarget, ProbToNewTarget);

217 ThisMBB->addSuccessor(NewMBB, ProbFallThrough);

218

219

221 TII->get(NewBROpcode))

223 .addMBB(NewBRTarget);

225 TII->get(PPC::B))

229

230

233 assert(FirstTerminator->getOperand(0).isReg() &&

234 "Can't update condition of unconditional branch.");

236 }

238 FirstTerminator->setDesc(TII->get(InvertedOpcode));

239

240

241

242 for (auto *Succ : NewMBB->successors()) {

244 }

246

247 LLVM_DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump());

250 return true;

251}

252

254 return MI.getNumOperands() == 3;

255}

256

258 return MI.getNumOperands() == 1;

259}

260

261

262

263

264

265

266static void

268 bool &InvertNewBranch, bool &InvertOrigBranch,

269 bool &TargetIsFallThrough) {

270

271

272

273

274 if (BROp == PPC::BC || BROp == PPC::BCLR) {

275

276 switch (CROp) {

277 default:

278 llvm_unreachable("Don't know how to handle this CR logical.");

279 case PPC::CROR:

280 InvertNewBranch = false;

281 InvertOrigBranch = false;

282 TargetIsFallThrough = false;

283 return;

284 case PPC::CRAND:

285 InvertNewBranch = true;

286 InvertOrigBranch = false;

287 TargetIsFallThrough = true;

288 return;

289 case PPC::CRNAND:

290 InvertNewBranch = true;

291 InvertOrigBranch = true;

292 TargetIsFallThrough = false;

293 return;

294 case PPC::CRNOR:

295 InvertNewBranch = false;

296 InvertOrigBranch = true;

297 TargetIsFallThrough = true;

298 return;

299 case PPC::CRORC:

300 InvertNewBranch = UsingDef1;

301 InvertOrigBranch = !UsingDef1;

302 TargetIsFallThrough = false;

303 return;

304 case PPC::CRANDC:

305 InvertNewBranch = !UsingDef1;

306 InvertOrigBranch = !UsingDef1;

307 TargetIsFallThrough = true;

308 return;

309 }

310 } else if (BROp == PPC::BCn || BROp == PPC::BCLRn) {

311

312 switch (CROp) {

313 default:

314 llvm_unreachable("Don't know how to handle this CR logical.");

315 case PPC::CROR:

316 InvertNewBranch = true;

317 InvertOrigBranch = false;

318 TargetIsFallThrough = true;

319 return;

320 case PPC::CRAND:

321 InvertNewBranch = false;

322 InvertOrigBranch = false;

323 TargetIsFallThrough = false;

324 return;

325 case PPC::CRNAND:

326 InvertNewBranch = false;

327 InvertOrigBranch = true;

328 TargetIsFallThrough = true;

329 return;

330 case PPC::CRNOR:

331 InvertNewBranch = true;

332 InvertOrigBranch = true;

333 TargetIsFallThrough = false;

334 return;

335 case PPC::CRORC:

336 InvertNewBranch = !UsingDef1;

337 InvertOrigBranch = !UsingDef1;

338 TargetIsFallThrough = true;

339 return;

340 case PPC::CRANDC:

341 InvertNewBranch = UsingDef1;

342 InvertOrigBranch = !UsingDef1;

343 TargetIsFallThrough = false;

344 return;

345 }

346 } else

348}

349

350namespace {

351

353

354public:

355 static char ID;

356 struct CRLogicalOpInfo {

358

359 std::pair<MachineInstr*, MachineInstr*> CopyDefs;

360 std::pair<MachineInstr*, MachineInstr*> TrueDefs;

361 unsigned IsBinary : 1;

362 unsigned IsNullary : 1;

363 unsigned ContainedInBlock : 1;

364 unsigned FeedsISEL : 1;

365 unsigned FeedsBR : 1;

366 unsigned FeedsLogical : 1;

367 unsigned SingleUse : 1;

368 unsigned DefsSingleUse : 1;

369 unsigned SubregDef1;

370 unsigned SubregDef2;

371 CRLogicalOpInfo() : MI(nullptr), IsBinary(0), IsNullary(0),

372 ContainedInBlock(0), FeedsISEL(0), FeedsBR(0),

373 FeedsLogical(0), SingleUse(0), DefsSingleUse(1),

374 SubregDef1(0), SubregDef2(0) { }

376 };

377

378private:

383

384

387 void collectCRLogicals();

388 bool handleCROp(unsigned Idx);

389 bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);

391 unsigned Opc = MI.getOpcode();

392 return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||

393 Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CRNOT ||

394 Opc == PPC::CREQV || Opc == PPC::CRANDC || Opc == PPC::CRORC ||

395 Opc == PPC::CRSET || Opc == PPC::CRUNSET || Opc == PPC::CR6SET ||

396 Opc == PPC::CR6UNSET;

397 }

398 bool simplifyCode() {

399 bool Changed = false;

400

401

402 for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)

403 Changed |= handleCROp(i);

404 return Changed;

405 }

406

407public:

410 }

411

412 MachineInstr *lookThroughCRCopy(unsigned Reg, unsigned &Subreg,

416 return false;

417

418

420 if (!STI.useCRBits())

421 return false;

422

424 collectCRLogicals();

425 return simplifyCode();

426 }

427 CRLogicalOpInfo createCRLogicalOpInfo(MachineInstr &MI);

432 }

433};

434

435#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

436LLVM_DUMP_METHOD void PPCReduceCRLogicals::CRLogicalOpInfo::dump() {

437 dbgs() << "CRLogicalOpMI: ";

439 dbgs() << "IsBinary: " << IsBinary << ", FeedsISEL: " << FeedsISEL;

440 dbgs() << ", FeedsBR: " << FeedsBR << ", FeedsLogical: ";

441 dbgs() << FeedsLogical << ", SingleUse: " << SingleUse;

442 dbgs() << ", DefsSingleUse: " << DefsSingleUse;

443 dbgs() << ", SubregDef1: " << SubregDef1 << ", SubregDef2: ";

444 dbgs() << SubregDef2 << ", ContainedInBlock: " << ContainedInBlock;

445 if (!IsNullary) {

446 dbgs() << "\nDefs:\n";

447 TrueDefs.first->dump();

448 }

449 if (IsBinary)

450 TrueDefs.second->dump();

451 dbgs() << "\n";

452 if (CopyDefs.first) {

453 dbgs() << "CopyDef1: ";

454 CopyDefs.first->dump();

455 }

456 if (CopyDefs.second) {

457 dbgs() << "CopyDef2: ";

458 CopyDefs.second->dump();

459 }

460}

461#endif

462

463PPCReduceCRLogicals::CRLogicalOpInfo

464PPCReduceCRLogicals::createCRLogicalOpInfo(MachineInstr &MIParam) {

465 CRLogicalOpInfo Ret;

466 Ret.MI = &MIParam;

467

469 Ret.IsNullary = 1;

470 Ret.TrueDefs = std::make_pair(nullptr, nullptr);

471 Ret.CopyDefs = std::make_pair(nullptr, nullptr);

472 } else {

474 Ret.SubregDef1, Ret.CopyDefs.first);

475 assert(Def1 && "Must be able to find a definition of operand 1.");

476 Ret.DefsSingleUse &=

478 Ret.DefsSingleUse &=

479 MRI->hasOneNonDBGUse(Ret.CopyDefs.first->getOperand(0).getReg());

481 Ret.IsBinary = 1;

483 Ret.SubregDef2,

484 Ret.CopyDefs.second);

485 assert(Def2 && "Must be able to find a definition of operand 2.");

486 Ret.DefsSingleUse &=

488 Ret.DefsSingleUse &=

489 MRI->hasOneNonDBGUse(Ret.CopyDefs.second->getOperand(0).getReg());

490 Ret.TrueDefs = std::make_pair(Def1, Def2);

491 } else {

492 Ret.TrueDefs = std::make_pair(Def1, nullptr);

493 Ret.CopyDefs.second = nullptr;

494 }

495 }

496

497 Ret.ContainedInBlock = 1;

498

501 unsigned Opc = UseMI.getOpcode();

502 if (Opc == PPC::ISEL || Opc == PPC::ISEL8)

503 Ret.FeedsISEL = 1;

504 if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR ||

505 Opc == PPC::BCLRn)

506 Ret.FeedsBR = 1;

507 Ret.FeedsLogical = isCRLogical(UseMI);

509 Ret.ContainedInBlock = 0;

510 }

512

513

514 if ( Ret .IsNullary) {

515 Ret.ContainedInBlock &=

516 (MIParam.getParent() == Ret.TrueDefs.first->getParent());

517 if (Ret.IsBinary)

518 Ret.ContainedInBlock &=

519 (MIParam.getParent() == Ret.TrueDefs.second->getParent());

520 }

522 if (Ret.IsBinary && Ret.ContainedInBlock && Ret.SingleUse) {

523 NumContainedSingleUseBinOps++;

524 if (Ret.FeedsBR && Ret.DefsSingleUse)

525 NumToSplitBlocks++;

526 }

527 return Ret;

528}

529

530

531

532

533

534

535

536MachineInstr *PPCReduceCRLogicals::lookThroughCRCopy(unsigned Reg,

537 unsigned &Subreg,

539 Subreg = -1;

541 return nullptr;

543 CpDef = Copy;

544 if ( Copy ->isCopy())

546 Register CopySrc = Copy->getOperand(1).getReg();

547 Subreg = Copy->getOperand(1).getSubReg();

550

551 if (CopySrc == PPC::CR0EQ || CopySrc == PPC::CR6EQ)

552 Subreg = PPC::sub_eq;

553 if (CopySrc == PPC::CR0LT || CopySrc == PPC::CR6LT)

554 Subreg = PPC::sub_lt;

555 if (CopySrc == PPC::CR0GT || CopySrc == PPC::CR6GT)

556 Subreg = PPC::sub_gt;

557 if (CopySrc == PPC::CR0UN || CopySrc == PPC::CR6UN)

558 Subreg = PPC::sub_un;

559

561 while (Me != B)

562 if ((--Me)->modifiesRegister(CopySrc, TRI))

563 return &*Me;

564 return nullptr;

565 }

566 return MRI->getVRegDef(CopySrc);

567}

568

569void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {

570 MF = &MFParam;

573 MBPI = &getAnalysis().getMBPI();

574

575 AllCRLogicalOps.clear();

576}

577

578

579

580

581

582

583bool PPCReduceCRLogicals::handleCROp(unsigned Idx) {

584

585

586 bool Changed = false;

587 CRLogicalOpInfo CRI = AllCRLogicalOps[Idx];

588 if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&

589 CRI.DefsSingleUse) {

590 Changed = splitBlockOnBinaryCROp(CRI);

591 if (Changed)

592 NumBlocksSplitOnBinaryCROp++;

593 }

594 return Changed;

595}

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

613

614bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) {

615 if (CRI.CopyDefs.first == CRI.CopyDefs.second) {

616 LLVM_DEBUG(dbgs() << "Unable to split as the two operands are the same\n");

617 NumNotSplitIdenticalOperands++;

618 return false;

619 }

620 if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() ||

621 CRI.TrueDefs.first->isPHI() || CRI.TrueDefs.second->isPHI()) {

623 dbgs() << "Unable to split because one of the operands is a PHI or "

624 "chain of copies.\n");

625 NumNotSplitChainCopies++;

626 return false;

627 }

628

629 if (CRI.MI->getOpcode() != PPC::CROR &&

630 CRI.MI->getOpcode() != PPC::CRAND &&

631 CRI.MI->getOpcode() != PPC::CRNOR &&

632 CRI.MI->getOpcode() != PPC::CRNAND &&

633 CRI.MI->getOpcode() != PPC::CRORC &&

634 CRI.MI->getOpcode() != PPC::CRANDC) {

635 LLVM_DEBUG(dbgs() << "Unable to split blocks on this opcode.\n");

636 NumNotSplitWrongOpcode++;

637 return false;

638 }

639 LLVM_DEBUG(dbgs() << "Splitting the following CR op:\n"; CRI.dump());

642

643 bool UsingDef1 = false;

645 for (auto E = CRI.MI->getParent()->end(); Def2It != E; ++Def2It) {

646 if (Def1It == Def2It) {

647 SplitBefore = &*Def1It;

648 UsingDef1 = true;

649 break;

650 }

651 }

652

653 LLVM_DEBUG(dbgs() << "We will split the following block:\n";);

654 LLVM_DEBUG(CRI.MI->getParent()->dump());

656

657

659 MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();

660

661

662

663

664

668 UsingDef1 ? CRI.TrueDefs.first : CRI.TrueDefs.second;

670 UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second;

671

672

673

674

675

676 MBB->splice(FirstTerminator, MBB, FirstInstrToMove);

677 if (FirstInstrToMove != SecondInstrToMove)

678 MBB->splice(FirstTerminator, MBB, SecondInstrToMove);

680

681 unsigned Opc = CRI.MI->getOpcode();

682 bool InvertOrigBranch, InvertNewBranch, TargetIsFallThrough;

684 InvertNewBranch, InvertOrigBranch,

685 TargetIsFallThrough);

687 UsingDef1 ? CRI.CopyDefs.second : CRI.CopyDefs.first;

688 LLVM_DEBUG(dbgs() << "We will " << (InvertNewBranch ? "invert" : "copy"));

689 LLVM_DEBUG(dbgs() << " the original branch and the target is the "

690 << (TargetIsFallThrough ? "fallthrough block\n"

691 : "orig. target block\n"));

694 InvertOrigBranch, TargetIsFallThrough, MBPI, CRI.MI,

695 UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second };

696 bool Changed = splitMBB(BSI);

697

698

699 if (Changed) {

700 bool Input1CRlogical =

701 CRI.TrueDefs.first && isCRLogical(*CRI.TrueDefs.first);

702 bool Input2CRlogical =

703 CRI.TrueDefs.second && isCRLogical(*CRI.TrueDefs.second);

704 if (Input1CRlogical)

705 AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.first));

706 if (Input2CRlogical)

707 AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.second));

708 }

709 return Changed;

710}

711

712void PPCReduceCRLogicals::collectCRLogicals() {

715 if (isCRLogical(MI)) {

716 AllCRLogicalOps.push_back(createCRLogicalOpInfo(MI));

717 TotalCRLogicals++;

718 if (AllCRLogicalOps.back().IsNullary)

719 TotalNullaryCRLogicals++;

720 else if (AllCRLogicalOps.back().IsBinary)

721 TotalBinaryCRLogicals++;

722 else

723 TotalUnaryCRLogicals++;

724 }

725 }

726 }

727}

728

729}

730

732 "PowerPC Reduce CR logical Operation", false, false)

736

737char PPCReduceCRLogicals::ID = 0;

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

MachineBasicBlock MachineBasicBlock::iterator MBBI

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

static bool isBinary(MachineInstr &MI)

PowerPC Reduce CR logical Operation

static bool isNullary(MachineInstr &MI)

static bool splitMBB(BlockSplitInfo &BSI)

Splits a MachineBasicBlock to branch before SplitBefore.

static void computeBranchTargetAndInversion(unsigned CROp, unsigned BROp, bool UsingDef1, bool &InvertNewBranch, bool &InvertOrigBranch, bool &TargetIsFallThrough)

Given a CR logical operation CROp, branch opcode BROp as well as a flag to indicate if the first oper...

static void addIncomingValuesToPHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB, MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI)

Given a basic block Successor that potentially contains PHIs, this function will look for PHIs that h...

static void updatePHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB, MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI)

Given a basic block Successor that potentially contains PHIs, this function will look for any incomin...

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringLiteral > StandardNames)

Initialize the set of available library functions based on the specified target triple.

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

LLVM Basic Block Representation.

static BranchProbability getUnknown()

BranchProbability getCompl() const

FunctionPass class - This class is used to implement most global optimizations.

bool skipFunction(const Function &F) const

Optional passes call this function to check whether the pass should be skipped.

void transferSuccessors(MachineBasicBlock *FromMBB)

Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

void setSuccProbability(succ_iterator I, BranchProbability Prob)

Set successor probability of a given iterator.

succ_iterator succ_begin()

iterator getFirstTerminator()

Returns an iterator to the first terminator instruction of this basic block.

unsigned succ_size() const

void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

succ_reverse_iterator succ_rbegin()

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

iterator_range< succ_iterator > successors()

bool isSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB is a successor of this block.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const

Analysis pass which computes a MachineDominatorTree.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineBasicBlock - Allocate a new MachineBasicBlock.

void insert(iterator MBBI, MachineBasicBlock *MBB)

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

MachineBasicBlock * getMBB() const

void setMBB(MachineBasicBlock *MBB)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

static constexpr bool isVirtualRegister(unsigned Reg)

Return true if the specified register number is in the virtual register namespace.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

auto find(R &&Range, const T &Val)

Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

void initializePPCReduceCRLogicalsPass(PassRegistry &)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionPass * createPPCReduceCRLogicalsPass()

MachineInstr * SplitBefore

MachineInstr * OrigBranch

MachineInstr * MIToDelete

bool allInstrsInSameMBB()

const MachineBranchProbabilityInfo * MBPI