PPCSubtarget.cpp Source File (original) (raw)

32#include

34using namespace llvm;

36#define DEBUG_TYPE "ppc-subtarget"

38#define GET_SUBTARGETINFO_TARGET_DESC

39#define GET_SUBTARGETINFO_CTOR

40#include "PPCGenSubtargetInfo.inc"

44 cl::desc("Enable Machine Pipeliner for PPC"),

50 initializeEnvironment();

51 initSubtargetFeatures(CPU, TuneCPU, FS);

52 return *this;

53}

56 const std::string &TuneCPU, const std::string &FS,

59 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||

60 TargetTriple.getArch() == Triple::ppc64le),

61 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),

62 InstrInfo(*this), TLInfo(TM, *this) {

63 TSInfo = std::make_unique();

71}

77}

79void PPCSubtarget::initializeEnvironment() {

83}

85void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,

88 std::string CPUName = std::string(CPU);

89 if (CPUName.empty() || CPU == "generic") {

91 CPUName = "e500";

92 else

94 }

97 if (TuneCPU.empty()) TuneCPU = CPUName;

100 InstrItins = getInstrItineraryForCPU(CPUName);

101

102

104

105

106

107 if (IsPPC64 && has64BitSupport())

108 Use64BitRegs = true;

109

111 IsSecurePlt = true;

112

114 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);

115 if (HasSPE && (HasAltivec || HasVSX || HasFPU))

117 "SPE and traditional floating point cannot both be enabled.\n", false);

118

119

120 if (!HasSPE)

121 HasFPU = true;

122

124

125

127

128 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {

130 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "

131 "only supported on AIX in "

132 "64-bit mode.\n",

133 false);

134

135

136

137

138

140 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "

141 "only be specified with "

142 "-data-sections.\n",

143 false);

144 }

145

148 "is only supported on AIX in 64-bit mode.\n",

149 false);

150}

151

153

156}

157

159

160

162

164 return TargetSubtargetInfo::ANTIDEP_ALL;

165}

166

168 CriticalPathRCs.clear();

169 CriticalPathRCs.push_back(isPPC64() ?

170 &PPC::G8RCRegClass : &PPC::GPRCRegClass);

171}

172

174 unsigned NumRegionInstrs) const {

175

176

177

178

179

181

182

184}

185

187 return true;

188}

189

191

194 if (const GlobalVariable *GVar = dyn_cast(GV))

195

196 return !GVar->hasAttribute("toc-data");

197

198 return true;

199 }

200

201

203 return true;

204

206 return false;

207 return true;

208}

209

212

213

215

216

218 return ModuleModel;

219

220

221

222 assert(GV && "Unexpected NULL GlobalValue");

225 const GlobalVariable *Var = dyn_cast(GV);

226 if (Var)

227 return Var;

228

229 const GlobalAlias *Alias = dyn_cast(GV);

230 if (Alias)

232

233 return nullptr;

234 }(GV);

235

236 if (!GlobalVar)

237 return ModuleModel;

238

239 std::optionalCodeModel::Model MaybeCodeModel = GlobalVar->getCodeModel();

240 if (MaybeCodeModel) {

243 "invalid code model for AIX");

244 return CM;

245 }

246

247 return ModuleModel;

248}

249

252

256}

257

258

261}

262

265}

266

269}

270

273}

static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)

This file describes how to lower LLVM calls to machine code calls.

This file declares the targeting of the Machinelegalizer class for PowerPC.

This file declares the targeting of the RegisterBankInfo class for PowerPC.

static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

const GlobalObject * getAliaseeObject() const

This class provides the information for the PowerPC target legalizer for GlobalISel.

std::unique_ptr< InstructionSelector > InstSelector

bool enableMachinePipeliner() const override

Pipeliner customization.

bool useDFAforSMS() const override

Machine Pipeliner customization.

const CallLowering * getCallLowering() const override

Triple TargetTriple

TargetTriple - What processor and OS we're targeting.

const LegalizerInfo * getLegalizerInfo() const override

std::unique_ptr< RegisterBankInfo > RegBankInfo

InstrItineraryData InstrItins

Selected instruction itineraries (one entry per itinerary class.)

Align StackAlignment

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...

void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override

bool isPPC64() const

isPPC64 - Return true if we are generating code for 64-bit pointer mode.

void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override

bool isUsingPCRelativeCalls() const

bool enableSubRegLiveness() const override

const PPCTargetLowering * getTargetLowering() const override

InstructionSelector * getInstructionSelector() const override

unsigned CPUDirective

Which cpu directive was used.

AntiDepBreakMode getAntiDepBreakMode() const override

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

bool useAA() const override

PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)

initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...

CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const

Calculates the effective code model for argument GV.

Align getPlatformStackAlignment() const

const PPCTargetMachine & getTargetMachine() const

PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const PPCTargetMachine &TM)

This constructor initializes the data members to match that of the specified triple.

const PPCTargetMachine & TM

std::unique_ptr< const SelectionDAGTargetInfo > TSInfo

bool enableMachineScheduler() const override

Scheduling customization.

const RegisterBankInfo * getRegBankInfo() const override

const PPCRegisterInfo * getRegisterInfo() const override

bool isGVIndirectSymbol(const GlobalValue *GV) const

True if the GV will be accessed via an indirect symbol.

std::unique_ptr< CallLowering > CallLoweringInfo

GlobalISel related APIs.

bool enablePostRAScheduler() const override

This overrides the PostRAScheduler bit in the SchedModel for each CPU.

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Common code between 32-bit and 64-bit PowerPC targets.

bool isLittleEndian() const

Holds all the information related to register banks.

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

Primary interface to the complete machine description for the target machine.

bool shouldAssumeDSOLocal(const GlobalValue *GV) const

bool getDataSections() const

Return true if data objects should be emitted into their own section, corresponds to -fdata-sections.

CodeModel::Model getCodeModel() const

Returns the code model.

Triple - Helper class for working with autoconf configuration names.

SubArchType getSubArch() const

get the parsed subarchitecture type for this triple.

bool isOSAIX() const

Tests whether the OS is AIX.

bool isPPC32SecurePlt() const

Tests whether the target 32-bit PowerPC uses Secure PLT.

StringRef getNormalizedPPCTargetCPU(const Triple &T, StringRef CPUName="")

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)

This struct is a compact representation of a valid (non-zero power of two) alignment.

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.