PPCSubtarget.cpp Source File (original) (raw)

32#include

34using namespace llvm;

36#define DEBUG_TYPE "ppc-subtarget"

38#define GET_SUBTARGETINFO_TARGET_DESC

39#define GET_SUBTARGETINFO_CTOR

40#include "PPCGenSubtargetInfo.inc"

44 cl::desc("Enable Machine Pipeliner for PPC"),

50 initializeEnvironment();

51 initSubtargetFeatures(CPU, TuneCPU, FS);

52 return *this;

53}

60 TSInfo = std::make_unique();

68}

76void PPCSubtarget::initializeEnvironment() {

80}

82void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,

85 std::string CPUName = std::string(CPU);

86 if (CPUName.empty() || CPU == "generic") {

88 CPUName = "e500";

89 else

91 }

94 if (TuneCPU.empty()) TuneCPU = CPUName;

97 InstrItins = getInstrItineraryForCPU(CPUName);

101

102

103

104 if (IsPPC64 && has64BitSupport())

105 Use64BitRegs = true;

106

107 if (getTargetTriple().isPPC32SecurePlt())

108 IsSecurePlt = true;

109

110 if (HasSPE && IsPPC64)

111 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);

112 if (HasSPE && (HasAltivec || HasVSX || HasFPU))

114 "SPE and traditional floating point cannot both be enabled.\n", false);

115

116

117 if (!HasSPE)

118 HasFPU = true;

119

121

122

124

125 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {

126 if (!getTargetTriple().isOSAIX() || !IsPPC64)

127 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "

128 "only supported on AIX in "

129 "64-bit mode.\n",

130 false);

131

132

133

134

135

136 if (.getDataSections())

137 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "

138 "only be specified with "

139 "-data-sections.\n",

140 false);

141 }

142

143 if (HasAIXShLibTLSModelOpt && (!getTargetTriple().isOSAIX() || !IsPPC64))

145 "is only supported on AIX in 64-bit mode.\n",

146 false);

147}

148

150

154

156

157

159

161 return TargetSubtargetInfo::ANTIDEP_ALL;

162}

163

165 CriticalPathRCs.clear();

166 CriticalPathRCs.push_back(isPPC64() ?

167 &PPC::G8RCRegClass : &PPC::GPRCRegClass);

168}

169

172

173

174

175

176

178

179

181}

182

186

188

192

193 return !GVar->hasAttribute("toc-data");

194

195 return true;

196 }

197

198

200 return true;

201

202 if (TM.shouldAssumeDSOLocal(GV))

203 return false;

204 return true;

205}

206

209

210

212

213

215 return ModuleModel;

216

217

218

219 assert(GV && "Unexpected NULL GlobalValue");

223 if (Var)

224 return Var;

225

227 if (Alias)

229

230 return nullptr;

231 }(GV);

232

233 if (!GlobalVar)

234 return ModuleModel;

235

236 std::optionalCodeModel::Model MaybeCodeModel = GlobalVar->getCodeModel();

237 if (MaybeCodeModel) {

240 "invalid code model for AIX");

241 return CM;

242 }

243

244 return ModuleModel;

245}

246

248

250 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&

252}

253

254

258

262

266

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)

This file describes how to lower LLVM calls to machine code calls.

This file declares the targeting of the Machinelegalizer class for PowerPC.

This file declares the targeting of the RegisterBankInfo class for PowerPC.

static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)

LLVM_ABI const GlobalObject * getAliaseeObject() const

This class provides the information for the PowerPC target legalizer for GlobalISel.

std::unique_ptr< InstructionSelector > InstSelector

bool enableMachinePipeliner() const override

Pipeliner customization.

Definition PPCSubtarget.cpp:151

bool useDFAforSMS() const override

Machine Pipeliner customization.

Definition PPCSubtarget.cpp:155

std::unique_ptr< LegalizerInfo > Legalizer

PPCFrameLowering FrameLowering

const CallLowering * getCallLowering() const override

Definition PPCSubtarget.cpp:255

const LegalizerInfo * getLegalizerInfo() const override

Definition PPCSubtarget.cpp:263

std::unique_ptr< RegisterBankInfo > RegBankInfo

InstrItineraryData InstrItins

Selected instruction itineraries (one entry per itinerary class.)

Align StackAlignment

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...

void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override

Definition PPCSubtarget.cpp:164

bool isUsingPCRelativeCalls() const

Definition PPCSubtarget.cpp:249

bool enableSubRegLiveness() const override

Definition PPCSubtarget.cpp:187

const PPCTargetLowering * getTargetLowering() const override

InstructionSelector * getInstructionSelector() const override

Definition PPCSubtarget.cpp:267

unsigned CPUDirective

Which cpu directive was used.

AntiDepBreakMode getAntiDepBreakMode() const override

Definition PPCSubtarget.cpp:160

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

Definition PPCSubtarget.cpp:72

bool useAA() const override

Definition PPCSubtarget.cpp:183

PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)

initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...

Definition PPCSubtarget.cpp:47

CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const

Calculates the effective code model for argument GV.

Definition PPCSubtarget.cpp:207

PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, const PPCTargetMachine &TM)

This constructor initializes the data members to match that of the specified triple.

Definition PPCSubtarget.cpp:55

bool isELFv2ABI() const

Definition PPCSubtarget.cpp:247

Align getPlatformStackAlignment() const

const PPCTargetMachine & getTargetMachine() const

const PPCTargetMachine & TM

std::unique_ptr< const SelectionDAGTargetInfo > TSInfo

bool enableMachineScheduler() const override

Scheduling customization.

Definition PPCSubtarget.cpp:149

void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override

Definition PPCSubtarget.cpp:170

const RegisterBankInfo * getRegBankInfo() const override

Definition PPCSubtarget.cpp:259

const PPCRegisterInfo * getRegisterInfo() const override

bool isGVIndirectSymbol(const GlobalValue *GV) const

True if the GV will be accessed via an indirect symbol.

Definition PPCSubtarget.cpp:189

std::unique_ptr< CallLowering > CallLoweringInfo

GlobalISel related APIs.

bool enablePostRAScheduler() const override

This overrides the PostRAScheduler bit in the SchedModel for each CPU.

Definition PPCSubtarget.cpp:158

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Common code between 32-bit and 64-bit PowerPC targets.

Holds all the information related to register banks.

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

constexpr bool empty() const

empty - Check if the string is empty.

Primary interface to the complete machine description for the target machine.

CodeModel::Model getCodeModel() const

Returns the code model.

Triple - Helper class for working with autoconf configuration names.

LLVM_ABI StringRef getNormalizedPPCTargetCPU(const Triple &T, StringRef CPUName="")

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)

This struct is a compact representation of a valid (non-zero power of two) alignment.

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

A region of an MBB for scheduling.