LLVM: lib/Target/PowerPC/PPCVSXSwapRemoval.cpp Source File (original) (raw)
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52#include "llvm/Config/llvm-config.h"
56
57using namespace llvm;
58
59#define DEBUG_TYPE "ppc-vsx-swaps"
60
61namespace {
62
63
64
65struct PPCVSXSwapEntry {
66
68
69
70 int VSEId;
71
72
73 unsigned int IsLoad : 1;
74 unsigned int IsStore : 1;
75 unsigned int IsSwap : 1;
76 unsigned int MentionsPhysVR : 1;
77 unsigned int IsSwappable : 1;
78 unsigned int MentionsPartialVR : 1;
79 unsigned int SpecialHandling : 3;
80 unsigned int WebRejected : 1;
81 unsigned int WillRemove : 1;
82};
83
84enum SHValues {
85 SH_NONE = 0,
86 SH_EXTRACT,
87 SH_INSERT,
88 SH_NOSWAP_LD,
89 SH_NOSWAP_ST,
90 SH_SPLAT,
91 SH_XXPERMDI,
92 SH_COPYWIDEN
93};
94
96
97 static char ID;
101
102
103 std::vector SwapVector;
104
105
106
108
109
110
112
114
115private:
116
118
119
120
121 bool gatherVectorInstructions();
122
123
124 int addSwapEntry(MachineInstr *MI, PPCVSXSwapEntry &SwapEntry);
125
126
127
128
129
130 unsigned lookThruCopyLike(unsigned SrcReg, unsigned VecIdx);
131
132
133 void formWebs();
134
135
136 void recordUnoptimizableWebs();
137
138
139 void markSwapsForRemoval();
140
141
142
143 bool removeSwaps();
144
145
146
148 unsigned DstReg, unsigned SrcReg);
149
150
151 void handleSpecialSwappables(int EntryIdx);
152
153
154 void dumpSwapVector();
155
156
161 }
162
163
167 }
168
169
170 bool isScalarVecReg(unsigned Reg) {
173 }
174
175
176
177
178 bool isAnyVecReg(unsigned Reg, bool &Partial) {
179 if (isScalarVecReg(Reg))
180 Partial = true;
182 }
183
184public:
185
186 bool runOnMachineFunction(MachineFunction &MF) override {
188 return false;
189
190
191
192
195 return false;
196
199
200 if (gatherVectorInstructions()) {
201 formWebs();
202 recordUnoptimizableWebs();
203 markSwapsForRemoval();
205 }
206
207
208 delete EC;
210 }
211};
212}
213
214
215
216
217void PPCVSXSwapRemoval::initialize(MachineFunction &MFParm) {
218 MF = &MFParm;
221
222
223
224
225
226 const int InitialVectorSize(256);
227 SwapVector.clear();
228 SwapVector.reserve(InitialVectorSize);
229
230
231
232
233 EC = new EquivalenceClasses;
234}
235
236
237
238
239bool PPCVSXSwapRemoval::gatherVectorInstructions() {
240 bool RelevantFunction = false;
241
242 for (MachineBasicBlock &MBB : *MF) {
243 for (MachineInstr &MI : MBB) {
244
245 if (MI.isDebugInstr())
246 continue;
247
248 bool RelevantInstr = false;
249 bool Partial = false;
250
251 for (const MachineOperand &MO : MI.operands()) {
252 if (!MO.isReg())
253 continue;
255
256
257
258 if (isAnyVecReg(Reg, Partial))
259 RelevantInstr = true;
260 }
261
262 if (!RelevantInstr)
263 continue;
264
265 RelevantFunction = true;
266
267
268
269
270 PPCVSXSwapEntry SwapEntry{};
271 int VecIdx = addSwapEntry(&MI, SwapEntry);
272
273 switch(MI.getOpcode()) {
274 default:
275
276
277
278
279
280
281 if (Partial)
282 SwapVector[VecIdx].MentionsPartialVR = 1;
283 else
284 SwapVector[VecIdx].IsSwappable = 1;
285 break;
286 case PPC::XXPERMDI: {
287
288
289
290
291
292
293
294 int immed = MI.getOperand(3).getImm();
295 if (immed == 2) {
296 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
297 VecIdx);
298 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
299 VecIdx);
300 if (trueReg1 == trueReg2)
301 SwapVector[VecIdx].IsSwap = 1;
302 else {
303
304
305 SwapVector[VecIdx].IsSwappable = 1;
306 SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
307 }
308
309
310
311
312
313
314
315
316 } else if (immed == 0 || immed == 3) {
317
318 SwapVector[VecIdx].IsSwappable = 1;
319 SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
320
321 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
322 VecIdx);
323 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
324 VecIdx);
325 if (trueReg1 == trueReg2)
326 SwapVector[VecIdx].MentionsPhysVR = 0;
327
328 } else {
329
330 SwapVector[VecIdx].IsSwappable = 1;
331 SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
332 }
333 break;
334 }
335 case PPC::LVX:
336
337
338
339
340 SwapVector[VecIdx].IsLoad = 1;
341 break;
342 case PPC::LXVD2X:
343 case PPC::LXVW4X:
344
345
346 SwapVector[VecIdx].IsLoad = 1;
347 SwapVector[VecIdx].IsSwap = 1;
348 break;
349 case PPC::LXSDX:
350 case PPC::LXSSPX:
351 case PPC::XFLOADf64:
352 case PPC::XFLOADf32:
353
354
355
356
357 SwapVector[VecIdx].IsLoad = 1;
358 SwapVector[VecIdx].IsSwappable = 1;
359 break;
360 case PPC::STVX:
361
362
363
364
365 SwapVector[VecIdx].IsStore = 1;
366 break;
367 case PPC::STXVD2X:
368 case PPC::STXVW4X:
369
370
371 SwapVector[VecIdx].IsStore = 1;
372 SwapVector[VecIdx].IsSwap = 1;
373 break;
374 case PPC::COPY:
375
376
377 if (isVecReg(MI.getOperand(0).getReg()) &&
379 SwapVector[VecIdx].IsSwappable = 1;
380
381
382
383
384 else if (isScalarVecReg(MI.getOperand(0).getReg()) &&
385 isScalarVecReg(MI.getOperand(1).getReg()))
386 SwapVector[VecIdx].IsSwappable = 1;
387 break;
388 case PPC::SUBREG_TO_REG: {
389
390
391
392
393
394
395
396 if (isVecReg(MI.getOperand(0).getReg()) &&
398 SwapVector[VecIdx].IsSwappable = 1;
399 else if (isVecReg(MI.getOperand(0).getReg()) &&
400 isScalarVecReg(MI.getOperand(2).getReg())) {
401 SwapVector[VecIdx].IsSwappable = 1;
402 SwapVector[VecIdx].SpecialHandling = SHValues::SH_COPYWIDEN;
403 }
404 break;
405 }
406 case PPC::VSPLTB:
407 case PPC::VSPLTH:
408 case PPC::VSPLTW:
409 case PPC::XXSPLTW:
410
411
412 SwapVector[VecIdx].IsSwappable = 1;
413 SwapVector[VecIdx].SpecialHandling = SHValues::SH_SPLAT;
414 break;
415
416
417
418
419
420
421
422
423 case PPC::INLINEASM:
424 case PPC::INLINEASM_BR:
425 case PPC::EXTRACT_SUBREG:
426 case PPC::INSERT_SUBREG:
427 case PPC::COPY_TO_REGCLASS:
428 case PPC::LVEBX:
429 case PPC::LVEHX:
430 case PPC::LVEWX:
431 case PPC::LVSL:
432 case PPC::LVSR:
433 case PPC::LVXL:
434 case PPC::STVEBX:
435 case PPC::STVEHX:
436 case PPC::STVEWX:
437 case PPC::STVXL:
438
439
440
441
442
443
444 case PPC::STXSDX:
445 case PPC::STXSSPX:
446 case PPC::VCIPHER:
447 case PPC::VCIPHERLAST:
448 case PPC::VMRGHB:
449 case PPC::VMRGHH:
450 case PPC::VMRGHW:
451 case PPC::VMRGLB:
452 case PPC::VMRGLH:
453 case PPC::VMRGLW:
454 case PPC::VMULESB:
455 case PPC::VMULESH:
456 case PPC::VMULESW:
457 case PPC::VMULEUB:
458 case PPC::VMULEUH:
459 case PPC::VMULEUW:
460 case PPC::VMULOSB:
461 case PPC::VMULOSH:
462 case PPC::VMULOSW:
463 case PPC::VMULOUB:
464 case PPC::VMULOUH:
465 case PPC::VMULOUW:
466 case PPC::VNCIPHER:
467 case PPC::VNCIPHERLAST:
468 case PPC::VPERM:
469 case PPC::VPERMXOR:
470 case PPC::VPKPX:
471 case PPC::VPKSHSS:
472 case PPC::VPKSHUS:
473 case PPC::VPKSDSS:
474 case PPC::VPKSDUS:
475 case PPC::VPKSWSS:
476 case PPC::VPKSWUS:
477 case PPC::VPKUDUM:
478 case PPC::VPKUDUS:
479 case PPC::VPKUHUM:
480 case PPC::VPKUHUS:
481 case PPC::VPKUWUM:
482 case PPC::VPKUWUS:
483 case PPC::VPMSUMB:
484 case PPC::VPMSUMD:
485 case PPC::VPMSUMH:
486 case PPC::VPMSUMW:
487 case PPC::VRLB:
488 case PPC::VRLD:
489 case PPC::VRLH:
490 case PPC::VRLW:
491 case PPC::VSBOX:
492 case PPC::VSHASIGMAD:
493 case PPC::VSHASIGMAW:
494 case PPC::VSL:
495 case PPC::VSLDOI:
496 case PPC::VSLO:
497 case PPC::VSR:
498 case PPC::VSRO:
499 case PPC::VSUM2SWS:
500 case PPC::VSUM4SBS:
501 case PPC::VSUM4SHS:
502 case PPC::VSUM4UBS:
503 case PPC::VSUMSWS:
504 case PPC::VUPKHPX:
505 case PPC::VUPKHSB:
506 case PPC::VUPKHSH:
507 case PPC::VUPKHSW:
508 case PPC::VUPKLPX:
509 case PPC::VUPKLSB:
510 case PPC::VUPKLSH:
511 case PPC::VUPKLSW:
512 case PPC::XXMRGHW:
513 case PPC::XXMRGLW:
514
515
516
517 case PPC::XXSLDWI:
518 case PPC::XSCVDPSPN:
519 case PPC::XSCVSPDPN:
520 case PPC::MTVSCR:
521 case PPC::MFVSCR:
522 break;
523 }
524 }
525 }
526
527 if (RelevantFunction) {
528 LLVM_DEBUG(dbgs() << "Swap vector when first built\n\n");
530 }
531
532 return RelevantFunction;
533}
534
535
536
537int PPCVSXSwapRemoval::addSwapEntry(MachineInstr *MI,
538 PPCVSXSwapEntry& SwapEntry) {
539 SwapEntry.VSEMI = MI;
540 SwapEntry.VSEId = SwapVector.size();
541 SwapVector.push_back(SwapEntry);
542 EC->insert(SwapEntry.VSEId);
543 SwapMap[MI] = SwapEntry.VSEId;
544 return SwapEntry.VSEId;
545}
546
547
548
549
550
551
552
553
554
555
556unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg,
557 unsigned VecIdx) {
558 MachineInstr *MI = MRI->getVRegDef(SrcReg);
559 if (->isCopyLike())
560 return SrcReg;
561
562 unsigned CopySrcReg;
563 if (MI->isCopy())
564 CopySrcReg = MI->getOperand(1).getReg();
565 else {
566 assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
567 CopySrcReg = MI->getOperand(2).getReg();
568 }
569
570 if (!Register::isVirtualRegister(CopySrcReg)) {
571 if (!isScalarVecReg(CopySrcReg))
572 SwapVector[VecIdx].MentionsPhysVR = 1;
573 return CopySrcReg;
574 }
575
576 return lookThruCopyLike(CopySrcReg, VecIdx);
577}
578
579
580
581
582
583
584
585
586void PPCVSXSwapRemoval::formWebs() {
587
588 LLVM_DEBUG(dbgs() << "\n*** Forming webs for swap removal ***\n\n");
589
590 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
591
592 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
593
594 LLVM_DEBUG(dbgs() << "\n" << SwapVector[EntryIdx].VSEId << " ");
596
597
598
599
600
601 for (const MachineOperand &MO : MI->operands()) {
602 if (!MO.isReg())
603 continue;
604
607 continue;
608
610 if (!(MI->isCopy() && isScalarVecReg(Reg)))
611 SwapVector[EntryIdx].MentionsPhysVR = 1;
612 continue;
613 }
614
615 if (!MO.isUse())
616 continue;
617
618 MachineInstr* DefMI = MRI->getVRegDef(Reg);
620 "Inconsistency: def of vector reg not found in swap map!");
621 int DefIdx = SwapMap[DefMI];
622 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
623 SwapVector[EntryIdx].VSEId);
624
626 SwapVector[DefIdx].VSEId,
627 SwapVector[EntryIdx].VSEId));
630 }
631 }
632}
633
634
635
636
637
638void PPCVSXSwapRemoval::recordUnoptimizableWebs() {
639
640 LLVM_DEBUG(dbgs() << "\n*** Rejecting webs for swap removal ***\n\n");
641
642 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
643 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
644
645
646 if (SwapVector[Repr].WebRejected)
647 continue;
648
649
650
651
652 if (SwapVector[EntryIdx].MentionsPhysVR ||
653 SwapVector[EntryIdx].MentionsPartialVR ||
654 !(SwapVector[EntryIdx].IsSwappable || SwapVector[EntryIdx].IsSwap)) {
655
656 SwapVector[Repr].WebRejected = 1;
657
659 dbgs() << format("Web %d rejected for physreg, partial reg, or not "
660 "swap[pable]\n",
661 Repr));
663 LLVM_DEBUG(SwapVector[EntryIdx].VSEMI->dump());
665 }
666
667
668
669 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
670 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
671 Register DefReg = MI->getOperand(0).getReg();
672
673
674
675
676
677 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
678 int UseIdx = SwapMap[&UseMI];
679
680 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
681 SwapVector[UseIdx].IsStore) {
682
683 SwapVector[Repr].WebRejected = 1;
684
686 "Web %d rejected for load not feeding swap\n", Repr));
692 }
693
694
695
696
697 if (SwapVector[UseIdx].IsSwap && !SwapVector[UseIdx].IsLoad &&
698 !SwapVector[UseIdx].IsStore) {
700 for (MachineInstr &UseOfUseMI :
701 MRI->use_nodbg_instructions(SwapDefReg)) {
702 int UseOfUseIdx = SwapMap[&UseOfUseMI];
703 if (SwapVector[UseOfUseIdx].IsStore) {
704 SwapVector[Repr].WebRejected = 1;
707 "Web %d rejected for load/swap feeding a store\n", Repr));
713 }
714 }
715 }
716 }
717
718
719
720 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
721 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
725 int DefIdx = SwapMap[DefMI];
726
727 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
728 SwapVector[DefIdx].IsStore) {
729
730 SwapVector[Repr].WebRejected = 1;
731
733 "Web %d rejected for store not fed by swap\n", Repr));
739 }
740
741
742
743 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
744 int UseIdx = SwapMap[&UseMI];
745
746 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) {
747 SwapVector[Repr].WebRejected = 1;
748
751 "Web %d rejected for swap not feeding only stores\n", Repr));
753 << " : ");
756 LLVM_DEBUG(SwapVector[UseIdx].VSEMI->dump());
758 }
759 }
760 }
761 }
762
763 LLVM_DEBUG(dbgs() << "Swap vector after web analysis:\n\n");
765}
766
767
768
769
770
771
772void PPCVSXSwapRemoval::markSwapsForRemoval() {
773
774 LLVM_DEBUG(dbgs() << "\n*** Marking swaps for removal ***\n\n");
775
776 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
777
778 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
779 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
780
781 if (!SwapVector[Repr].WebRejected) {
782 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
783 Register DefReg = MI->getOperand(0).getReg();
784
785 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
786 int UseIdx = SwapMap[&UseMI];
787 SwapVector[UseIdx].WillRemove = 1;
788
789 LLVM_DEBUG(dbgs() << "Marking swap fed by load for removal: ");
791 }
792 }
793
794 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
795 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
796
797 if (!SwapVector[Repr].WebRejected) {
798 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
801 int DefIdx = SwapMap[DefMI];
802 SwapVector[DefIdx].WillRemove = 1;
803
804 LLVM_DEBUG(dbgs() << "Marking swap feeding store for removal: ");
806 }
807
808 } else if (SwapVector[EntryIdx].IsSwappable &&
809 SwapVector[EntryIdx].SpecialHandling != 0) {
810 int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
811
812 if (!SwapVector[Repr].WebRejected)
813 handleSpecialSwappables(EntryIdx);
814 }
815 }
816}
817
818
819
820
821
822
823void PPCVSXSwapRemoval::insertSwap(MachineInstr *MI,
825 unsigned DstReg, unsigned SrcReg) {
826 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
827 TII->get(PPC::XXPERMDI), DstReg)
831}
832
833
834
835
836
837
838void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
839 switch (SwapVector[EntryIdx].SpecialHandling) {
840
841 default:
843
844
845
846 case SHValues::SH_SPLAT: {
847 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
848 unsigned NElts;
849
852
853 switch (MI->getOpcode()) {
854 default:
856 case PPC::VSPLTB: NElts = 16; break;
857 case PPC::VSPLTH: NElts = 8; break;
858 case PPC::VSPLTW:
859 case PPC::XXSPLTW: NElts = 4; break;
860 }
861
862 unsigned EltNo;
863 if (MI->getOpcode() == PPC::XXSPLTW)
864 EltNo = MI->getOperand(2).getImm();
865 else
866 EltNo = MI->getOperand(1).getImm();
867
868 EltNo = (EltNo + NElts / 2) % NElts;
869 if (MI->getOpcode() == PPC::XXSPLTW)
870 MI->getOperand(2).setImm(EltNo);
871 else
872 MI->getOperand(1).setImm(EltNo);
873
876 break;
877 }
878
879
880
881
882
883
884
885 case SHValues::SH_XXPERMDI: {
886 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
887
890
891 unsigned Selector = MI->getOperand(3).getImm();
892 if (Selector == 0 || Selector == 3)
893 Selector = 3 - Selector;
894 MI->getOperand(3).setImm(Selector);
895
896 Register Reg1 = MI->getOperand(1).getReg();
897 Register Reg2 = MI->getOperand(2).getReg();
898 MI->getOperand(1).setReg(Reg2);
899 MI->getOperand(2).setReg(Reg1);
900
901
902 bool IsKill1 = MI->getOperand(1).isKill();
903 bool IsKill2 = MI->getOperand(2).isKill();
904 MI->getOperand(1).setIsKill(IsKill2);
905 MI->getOperand(2).setIsKill(IsKill1);
906
909 break;
910 }
911
912
913
914
915 case SHValues::SH_COPYWIDEN: {
916 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
917
920
921 Register DstReg = MI->getOperand(0).getReg();
922 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
923 Register NewVReg = MRI->createVirtualRegister(DstRC);
924
925 MI->getOperand(0).setReg(NewVReg);
928
930
931
932
933
934
935
936 if (DstRC == &PPC::VRRCRegClass) {
937 Register VSRCTmp1 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
938 Register VSRCTmp2 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
939
940 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
941 TII->get(PPC::COPY), VSRCTmp1)
944
945 insertSwap(MI, InsertPoint, VSRCTmp2, VSRCTmp1);
947
948 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
949 TII->get(PPC::COPY), DstReg)
952
953 } else {
954 insertSwap(MI, InsertPoint, DstReg, NewVReg);
956 }
957 break;
958 }
959 }
960}
961
962
963
964bool PPCVSXSwapRemoval::removeSwaps() {
965
966 LLVM_DEBUG(dbgs() << "\n*** Removing swaps ***\n\n");
967
969
970 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
971 if (SwapVector[EntryIdx].WillRemove) {
973 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
974 MachineBasicBlock *MBB = MI->getParent();
976 MI->getOperand(0).getReg())
978
980 SwapVector[EntryIdx].VSEId));
982
983 MI->eraseFromParent();
984 }
985 }
986
988}
989
990#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
991
993
994 for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
995
996 MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
997 int ID = SwapVector[EntryIdx].VSEId;
998
1000 dbgs() << format("%6d", EC->getLeaderValue(ID));
1001 dbgs() << format(" %bb.%3d", MI->getParent()->getNumber());
1003
1004 if (SwapVector[EntryIdx].IsLoad)
1005 dbgs() << "load ";
1006 if (SwapVector[EntryIdx].IsStore)
1007 dbgs() << "store ";
1008 if (SwapVector[EntryIdx].IsSwap)
1009 dbgs() << "swap ";
1010 if (SwapVector[EntryIdx].MentionsPhysVR)
1011 dbgs() << "physreg ";
1012 if (SwapVector[EntryIdx].MentionsPartialVR)
1013 dbgs() << "partialreg ";
1014
1015 if (SwapVector[EntryIdx].IsSwappable) {
1016 dbgs() << "swappable ";
1017 switch(SwapVector[EntryIdx].SpecialHandling) {
1018 default:
1019 dbgs() << "special:**unknown**";
1020 break;
1021 case SH_NONE:
1022 break;
1023 case SH_EXTRACT:
1024 dbgs() << "special:extract ";
1025 break;
1026 case SH_INSERT:
1027 dbgs() << "special:insert ";
1028 break;
1029 case SH_NOSWAP_LD:
1030 dbgs() << "special:load ";
1031 break;
1032 case SH_NOSWAP_ST:
1033 dbgs() << "special:store ";
1034 break;
1035 case SH_SPLAT:
1036 dbgs() << "special:splat ";
1037 break;
1038 case SH_XXPERMDI:
1039 dbgs() << "special:xxpermdi ";
1040 break;
1041 case SH_COPYWIDEN:
1042 dbgs() << "special:copywiden ";
1043 break;
1044 }
1045 }
1046
1047 if (SwapVector[EntryIdx].WebRejected)
1048 dbgs() << "rejected ";
1049 if (SwapVector[EntryIdx].WillRemove)
1050 dbgs() << "remove ";
1051
1052 dbgs() << "\n";
1053
1054
1055 (void)MI;
1056 (void)ID;
1057 }
1058
1059 dbgs() << "\n";
1060}
1061#endif
1062
1064 "PowerPC VSX Swap Removal", false, false)
1067
1068char PPCVSXSwapRemoval::ID = 0;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
const TargetInstrInfo & TII
static bool isRegInClass(const MachineOperand &MO, const TargetRegisterClass *Class)
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This file defines the DenseMap class.
Generic implementation of equivalence classes through the use Tarjan's efficient union-find algorithm...
static Register UseReg(const MachineOperand &MO)
static bool isVecReg(unsigned Reg)
Promote Memory to Register
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, const llvm::StringTable &StandardNames, VectorLibrary VecLib)
Initialize the set of available library functions based on the specified target triple.
EquivalenceClasses - This represents a collection of equivalence classes and supports three efficient...
FunctionPass class - This class is used to implement most global optimizations.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
MachineInstrBundleIterator< MachineInstr > iterator
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
LLVM_ABI void dump() const
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool needsSwapsForVSXMemOps() const
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
std::string str() const
str - Get the contents as an std::string.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createPPCVSXSwapRemovalPass()
Definition PPCVSXSwapRemoval.cpp:1070
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.