ProcessImplicitDefs.cpp Source File (original) (raw)

22using namespace llvm;

24#define DEBUG_TYPE "processimpdefs"

26namespace {

39public:

40 static char ID;

44 }

52 MachineFunctionProperties::Property::IsSSA);

53 }

54};

55}

57char ProcessImplicitDefs::ID = 0;

61 "Process Implicit Definitions", false, false)

63void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {

64 AU.setPreservesCFG();

67}

69bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {

70 if (->isCopyLike() &&

71 ->isInsertSubreg() &&

72 ->isRegSequence() &&

73 ->isPHI())

74 return false;

76 if (MO.readsReg())

77 return false;

78 return true;

79}

81void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {

85 if (Reg.isVirtual()) {

89 MO.setIsUndef();

91 if (!canTurnIntoImplicitDef(UserMI))

92 continue;

93 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);

94 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));

95 WorkList.insert(UserMI);

96 }

97 MI->eraseFromParent();

98 return;

99 }

100

101

102

105 bool Found = false;

106 for (++UserMI; UserMI != UserE; ++UserMI) {

108 if (!MO.isReg())

109 continue;

110 Register UserReg = MO.getReg();

111 if (!UserReg.isPhysical() || TRI ->regsOverlap(Reg, UserReg))

112 continue;

113

114 Found = true;

115 if (MO.isUse())

116 MO.setIsUndef();

117 }

118 if (Found)

119 break;

120 }

121

122

123 if (Found) {

125 MI->eraseFromParent();

126 return;

127 }

128

129

130

131 for (unsigned i = MI->getNumOperands() - 1; i; --i)

132 MI->removeOperand(i);

134}

135

136

137

138bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {

139

140 LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"

141 << "********** Function: " << MF.getName() << '\n');

142

143 bool Changed = false;

144

148 assert(WorkList.empty() && "Inconsistent worklist state");

149

151

153 if (MI.isImplicitDef())

154 WorkList.insert(&MI);

155

156 if (WorkList.empty())

157 continue;

158

160 << " implicit defs.\n");

161 Changed = true;

162

163

164 do processImplicitDef(WorkList.pop_back_val());

165 while (!WorkList.empty());

166 }

167 return Changed;

168}

unsigned const MachineRegisterInfo * MRI

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file implements a set that has insertion order iteration characteristics.

A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.

Represent the analysis usage information of a pass.

Instructions::iterator instr_iterator

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

virtual MachineFunctionProperties getRequiredProperties() const

Properties which a MachineFunction may have at a given point in time.

MachineFunctionProperties & set(Property P)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Representation of each machine instruction.

const MachineBasicBlock * getParent() const

void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

A SetVector that performs no allocations if smaller than a certain size.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

virtual const TargetInstrInfo * getInstrInfo() const

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Reg

All possible values of the reg field in the ModR/M byte.

This is an optimization pass for GlobalISel generic memory operations.

void initializeProcessImplicitDefsPass(PassRegistry &)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

char & ProcessImplicitDefsID

ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.

Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.