R600Subtarget.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H

15#define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H

23#define GET_SUBTARGETINFO_HEADER

24#include "R600GenSubtargetInfo.inc"

26namespace llvm {

30private:

33 bool FMA = false;

34 bool CaymanISA = false;

35 bool CFALUBug = false;

36 bool HasVertexCache = false;

37 bool R600ALUInst = false;

38 bool FP64 = false;

39 short TexVTXClauseSize = 0;

43 std::unique_ptr TSInfo;

45public:

54 return &FrameLowering;

55 }

62 return &InstrInfo.getRegisterInfo();

63 }

66 return &InstrItins;

67 }

91 if (Size == 32)

94 return false;

95 }

100

104

106 return CaymanISA;

107 }

108

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117 bool hasFMA() const { return FMA; }

118

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151 unsigned

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165 return false;

166 }

167};

168

169}

170

171#endif

Base class for AMDGPU specific classes of TargetSubtarget.

R600 DAG Lowering interface definition.

Interface definition for R600InstrInfo.

AMDGPUSubtarget(Triple TT)

Itinerary data supplied by a subtarget to be used by a target.

Definition R600Subtarget.h:29

bool hasVertexCache() const

Definition R600Subtarget.h:121

bool hasFFBH() const

Definition R600Subtarget.h:113

bool hasCFAluBug() const

Definition R600Subtarget.h:119

unsigned getMinFlatWorkGroupSize() const override

Definition R600Subtarget.h:140

unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override

Definition R600Subtarget.h:135

bool hasFMA() const

Definition R600Subtarget.h:117

short getTexVTXClauseSize() const

Definition R600Subtarget.h:123

unsigned getMaxFlatWorkGroupSize() const override

Definition R600Subtarget.h:145

bool hasBFI() const

Definition R600Subtarget.h:86

R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)

unsigned getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override

Definition R600Subtarget.h:152

const R600FrameLowering * getFrameLowering() const override

Definition R600Subtarget.h:53

bool hasCaymanISA() const

Definition R600Subtarget.h:105

bool requiresDisjointEarlyClobberAndUndef() const override

Definition R600Subtarget.h:162

unsigned getMinWavesPerEU() const override

Definition R600Subtarget.h:158

bool hasCARRY() const

Definition R600Subtarget.h:101

const R600TargetLowering * getTargetLowering() const override

Definition R600Subtarget.h:57

const R600RegisterInfo * getRegisterInfo() const override

Definition R600Subtarget.h:61

~R600Subtarget() override

const R600InstrInfo * getInstrInfo() const override

Definition R600Subtarget.h:51

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

bool enableSubRegLiveness() const override

Definition R600Subtarget.h:129

R600Subtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)

bool hasBCNT(unsigned Size) const

Definition R600Subtarget.h:90

bool hasBORROW() const

Definition R600Subtarget.h:97

bool hasFFBL() const

Definition R600Subtarget.h:109

Align getStackAlignment() const

Definition R600Subtarget.h:77

bool hasBFE() const

Definition R600Subtarget.h:82

Generation getGeneration() const

Definition R600Subtarget.h:73

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

const InstrItineraryData * getInstrItineraryData() const override

Definition R600Subtarget.h:65

bool enableMachineScheduler() const override

Definition R600Subtarget.h:125

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

Primary interface to the complete machine description for the target machine.

Triple - Helper class for working with autoconf configuration names.

unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)

unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)

unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)

unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)

This is an optimization pass for GlobalISel generic memory operations.

This struct is a compact representation of a valid (non-zero power of two) alignment.