R600TargetTransformInfo.cpp Source File (original) (raw)

22using namespace llvm;

24#define DEBUG_TYPE "R600tti"

29 TLI(ST->getTargetLowering()), CommonTTI(TM, F) {}

36 bool Vec = ClassID == 1;

38}

50 return 128;

53 return 64;

55 return 32;

61 return 128;

63}

67 unsigned AddrSpace) const {

72}

76 unsigned AddrSpace) const {

78}

82 unsigned AddrSpace) const {

84}

90 return 1;

92 return 8;

93}

99 return Opcode == Instruction::PHI ? 0 : 1;

100

101

102 switch (Opcode) {

103 case Instruction::Br:

104 case Instruction::Ret:

105 return 10;

106 default:

108 }

109}

110

113 unsigned Index,

114 const Value *Op0,

115 const Value *Op1) const {

116 switch (Opcode) {

117 case Instruction::ExtractElement:

118 case Instruction::InsertElement: {

119 unsigned EltSize =

121 if (EltSize < 32) {

123 Op1);

124 }

125

126

127

128

129

130

131 return Index == ~0u ? 2 : 0;

132 }

133 default:

135 }

136}

137

141 CommonTTI.getUnrollingPreferences(L, SE, UP, ORE);

142}

143

146 CommonTTI.getPeelingPreferences(L, SE, PP);

147}

The AMDGPU TargetMachine interface definition for hw codegen targets.

static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))

AMDGPU R600 specific subclass of TargetSubtarget.

This file a TargetTransformInfoImplBase conforming object specific to the R600 target machine.

InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, const Value *Op0, const Value *Op1) const override

InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override

constexpr bool isScalar() const

Exactly one element.

Represents a single loop in the control flow graph.

InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, const Value *Op0, const Value *Op1) const override

Definition R600TargetTransformInfo.cpp:111

bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const

Definition R600TargetTransformInfo.cpp:65

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const override

Definition R600TargetTransformInfo.cpp:138

bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const override

Definition R600TargetTransformInfo.cpp:80

unsigned getMinVectorRegisterBitWidth() const override

Definition R600TargetTransformInfo.cpp:45

unsigned getMaxInterleaveFactor(ElementCount VF) const override

Definition R600TargetTransformInfo.cpp:86

unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override

Definition R600TargetTransformInfo.cpp:47

R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)

Definition R600TargetTransformInfo.cpp:26

unsigned getHardwareNumberOfRegisters(bool Vec) const

Definition R600TargetTransformInfo.cpp:31

InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override

Definition R600TargetTransformInfo.cpp:95

bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const override

Definition R600TargetTransformInfo.cpp:74

void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP) const override

Definition R600TargetTransformInfo.cpp:144

TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override

Definition R600TargetTransformInfo.cpp:41

unsigned getNumberOfRegisters(unsigned ClassID) const override

Definition R600TargetTransformInfo.cpp:35

The main scalar evolution driver.

virtual const DataLayout & getDataLayout() const

TargetCostKind

The kind of cost model.

@ TCK_CodeSize

Instruction code size.

@ TCK_SizeAndLatency

The weighted sum of size and latency.

static constexpr TypeSize getFixed(ScalarTy ExactSize)

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ PARAM_D_ADDRESS

end Internal address spaces.

@ REGION_ADDRESS

Address space for region memory. (GDS)

@ LOCAL_ADDRESS

Address space for local memory.

@ PARAM_I_ADDRESS

Address space for indirect addressable parameter memory (VTX1).

@ CONSTANT_ADDRESS

Address space for constant memory (VTX2).

@ GLOBAL_ADDRESS

Address space for global memory (RAT0, VTX0).

@ PRIVATE_ADDRESS

Address space for private memory.

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Parameters that control the generic loop unrolling transformation.