R600TargetTransformInfo.h Source File (original) (raw)

17#ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H

18#define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H

23namespace llvm {

32 friend BaseT;

38public:

56 unsigned AddrSpace) const;

58 unsigned AddrSpace) const override;

60 unsigned AddrSpace) const override;

63 const Instruction *I = nullptr) const override;

67 unsigned Index, const Value *Op0,

68 const Value *Op1) const override;

69};

71}

73#endif

This file a TargetTransformInfoImplBase conforming object specific to the AMDGPU target machine.

This file provides a helper that implements much of the TTI interface in terms of the target-independ...

static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))

InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, const Value *Op0, const Value *Op1) const override

BasicTTIImplBase(const TargetMachine *TM, const DataLayout &DL)

Represents a single loop in the control flow graph.

InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, const Value *Op0, const Value *Op1) const override

bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const override

bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const override

unsigned getMinVectorRegisterBitWidth() const override

const R600Subtarget * getST() const

Definition R600TargetTransformInfo.h:41

const AMDGPUTargetLowering * getTLI() const

Definition R600TargetTransformInfo.h:42

unsigned getMaxInterleaveFactor(ElementCount VF) const override

unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override

R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)

unsigned getHardwareNumberOfRegisters(bool Vec) const

InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const override

bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const override

void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP) const override

TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override

unsigned getNumberOfRegisters(unsigned ClassID) const override

The main scalar evolution driver.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

TargetCostKind

The kind of cost model.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

This is an optimization pass for GlobalISel generic memory operations.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Parameters that control the generic loop unrolling transformation.