LLVM: lib/CodeGen/RDFRegisters.cpp Source File (original) (raw)
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21#include
22#include
23#include
24#include
25
27
30 : TRI(tri) {
31 RegInfos.resize(TRI.getNumRegs());
32
33 BitVector BadRC(TRI.getNumRegs());
35 for (MCPhysReg R : *RC) {
36 RegInfo &RI = RegInfos[R];
37 if (RI.RegClass != nullptr && !BadRC[R]) {
38 if (RC->LaneMask != RI.RegClass->LaneMask) {
39 BadRC.set(R);
40 RI.RegClass = nullptr;
41 }
42 } else
43 RI.RegClass = RC;
44 }
45 }
46
47 UnitInfos.resize(TRI.getNumRegUnits());
48
49 for (MCRegUnit U : TRI.regunits()) {
50 if (UnitInfos[U].Reg != 0)
51 continue;
52 MCRegUnitRootIterator R(U, &TRI);
53 assert(R.isValid());
54 RegisterId F = *R;
55 ++R;
56 if (R.isValid()) {
57 UnitInfos[U].Mask = LaneBitmask::getAll();
58 UnitInfos[U].Reg = F;
59 } else {
60 for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
61 std::pair<MCRegUnit, LaneBitmask> P = *I;
62 UnitInfo &UI = UnitInfos[P.first];
63 UI.Reg = F;
64 UI.Mask = P.second;
65 }
66 }
67 }
68
69 for (const uint32_t *RM : TRI.getRegMasks())
70 RegMasks.insert(RM);
71 for (const MachineBasicBlock &B : mf)
72 for (const MachineInstr &In : B)
73 for (const MachineOperand &Op : In.operands())
75 RegMasks.insert(Op.getRegMask());
76
77 MaskInfos.resize(RegMasks.size() + 1);
78 for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) {
79 BitVector PU(TRI.getNumRegUnits());
80 const uint32_t *MB = RegMasks.get(M);
81 for (unsigned I = 1, E = TRI.getNumRegs(); I != E; ++I) {
82 if (!(MB[I / 32] & (1u << (I % 32))))
83 continue;
84 for (MCRegUnit Unit : TRI.regunits(MCRegister::from(I)))
85 PU.set(static_cast(Unit));
86 }
87 MaskInfos[M].Units = PU.flip();
88 }
89
90 AliasInfos.resize(TRI.getNumRegUnits());
91 for (MCRegUnit U : TRI.regunits()) {
92 BitVector AS(TRI.getNumRegs());
93 for (MCRegUnitRootIterator R(U, &TRI); R.isValid(); ++R)
94 for (MCPhysReg S : TRI.superregs_inclusive(*R))
95 AS.set(S);
96 AliasInfos[U].Regs = AS;
97 }
98}
99
103
105
106 std::set AS;
109
111 for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
112 if (MB[i / 32] & (1u << (i % 32)))
113 continue;
114 AS.insert(i);
115 }
116 return AS;
117 }
118
121 AS.insert(*AI);
122
123 return AS;
124}
125
127 std::set Units;
128
129 if (RR.isReg()) {
131 return Units;
133 auto [U, M] = *UM;
134 if ((M & RR.Mask).any())
135 Units.insert(static_cast<unsigned>(U));
136 }
137 return Units;
138 }
139
141 unsigned NumRegs = TRI.getNumRegs();
143 for (unsigned I = 0, E = (NumRegs + 31) / 32; I != E; ++I) {
145 if (I == 0)
147 if (I + 1 == E && NumRegs % 32 != 0)
149 if (C == 0)
150 continue;
151 while (C != 0) {
154 for (MCRegUnit U : TRI.regunits(CR))
155 Units.insert(static_cast<unsigned>(U));
157 }
158 }
159 return Units;
160}
161
163 if (RR.Id == R)
164 return RR;
165 if (unsigned Idx = TRI.getSubRegIndex(RegisterRef(R).asMCReg(), RR.asMCReg()))
166 return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask));
167 if (unsigned Idx =
169 const RegInfo &RI = RegInfos[R];
172 LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask);
174 }
176}
177
179 if (.isReg() ||
.isReg()) {
180
182 }
183
186
187
191 auto [AReg, AMask] = *AI;
192 auto [BReg, BMask] = *BI;
193
194
195
196 if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) {
197 if (AReg != BReg)
198 return false;
199
200 ++AI;
201 ++BI;
202 continue;
203 }
204
205 if ((AMask & A.Mask).none())
206 ++AI;
207 if ((BMask & B.Mask).none())
208 ++BI;
209 }
210
211 return static_cast<int>(AI.isValid()) == static_cast<int>(BI.isValid());
212}
213
215 if (.isReg() ||
.isReg()) {
216
218 }
219
224
225
229 auto [AReg, AMask] = *AI;
230 auto [BReg, BMask] = *BI;
231
232
233
234 if ((AMask & A.Mask).any() && (BMask & B.Mask).any()) {
235 if (AReg != BReg)
236 return AReg < BReg;
237
238 ++AI;
239 ++BI;
240 continue;
241 }
242
243 if ((AMask & A.Mask).none())
244 ++AI;
245 if ((BMask & B.Mask).none())
246 ++BI;
247 }
248
249 return static_cast<int>(AI.isValid()) < static_cast<int>(BI.isValid());
250}
251
253 if (A.isReg()) {
255 if (Reg && Reg.id() < TRI.getNumRegs())
256 OS << TRI.getName(Reg);
257 else
260 } else if (A.isUnit()) {
262 } else {
263 unsigned Idx = A.asMaskIdx();
264 const char *Fmt = Idx < 0x10000 ? "%04x" : "%08x";
265 OS << "M#" << format(Fmt, Idx);
266 }
267}
268
270 OS << '{';
271 for (unsigned U : A.units())
272 OS << ' ' << printRegUnit(static_cast(U), &TRI);
273 OS << " }";
274}
275
278 return Units.anyCommon(PRI.getMaskUnits(RR));
279
281 auto [Unit, LaneMask] = *U;
282 if ((LaneMask & RR.Mask).any())
283 if (Units.test(static_cast<unsigned>(Unit)))
284 return true;
285 }
286 return false;
287}
288
292 return T.reset(Units).none();
293 }
294
296 auto [Unit, LaneMask] = *U;
297 if ((LaneMask & RR.Mask).any())
298 if (!Units.test(static_cast<unsigned>(Unit)))
299 return false;
300 }
301 return true;
302}
303
306 Units |= PRI.getMaskUnits(RR);
307 return *this;
308 }
309
311 auto [Unit, LaneMask] = *U;
312 if ((LaneMask & RR.Mask).any())
313 Units.set(static_cast<unsigned>(Unit));
314 }
315 return *this;
316}
317
319 Units |= RG.Units;
320 return *this;
321}
322
326
328 Units &= RG.Units;
329 return *this;
330}
331
335
337 Units.reset(RG.Units);
338 return *this;
339}
340
343 T.insert(RR).intersect(*this);
344 if (T.empty())
348 return NR;
349}
350
352 return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef();
353}
354
356 int U = Units.find_first();
357 if (U < 0)
359
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363
364 BitVector Regs = PRI.getUnitAliases(static_cast<MCRegUnit>(U));
366
367
368
369 while (U >= 0) {
370 Regs &= PRI.getUnitAliases(static_cast<MCRegUnit>(U));
372 }
373
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375
376
377
379 if (F <= 0)
381
384 auto [Unit, LaneMask] = *I;
385 if (Units.test(static_cast<unsigned>(Unit)))
386 M |= LaneMask;
387 }
389}
390
392 : Owner(&RG) {
394 RegisterRef R = RG.PRI.getRefForUnit(static_cast(U));
395 Masks[R.Id] |= R.Mask;
396 }
397 Pos = End ? Masks.end() : Masks.begin();
398 Index = End ? Masks.size() : 0;
399}
400
403 return OS;
404}
405
407 if (P.Mask.all())
408 return OS;
409 if (P.Mask.none())
410 return OS << ":*none*";
411
413 if ((Val & 0xffff) == Val)
414 return OS << ':' << format("%04llX", Val);
415 if ((Val & 0xffffffff) == Val)
416 return OS << ':' << format("%08llX", Val);
418}
419
420}
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements the BitVector class.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
A common definition of LaneBitmask for use in TableGen and CodeGen.
Register const TargetRegisterInfo * TRI
static Interval intersect(const Interval &I1, const Interval &I2)
SI optimize exec mask operations pre RA
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
bool isValid() const
Returns true if this iterator is not yet at the end.
Wrapper class representing physical registers. Should be passed by value.
const LaneBitmask LaneMask
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
bool disjoint(const std::set< T > &A, const std::set< T > &B)
constexpr T maskLeadingOnes(unsigned N)
Create a bitmask with the N left-most bits set to 1, and all other bits set to 0.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
DWARFExpression::Operation Op
constexpr T maskTrailingOnes(unsigned N)
Create a bitmask with the N right-most bits set to 1, and all other bits set to 0.
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static constexpr LaneBitmask getAll()
constexpr bool none() const
PhysicalRegisterInfo(const TargetRegisterInfo &tri, const MachineFunction &mf)
Definition RDFRegisters.cpp:28
void print(raw_ostream &OS, RegisterRef A) const
Definition RDFRegisters.cpp:252
const TargetRegisterInfo & getTRI() const
bool equal_to(RegisterRef A, RegisterRef B) const
Definition RDFRegisters.cpp:178
const uint32_t * getRegMaskBits(RegisterRef RR) const
bool alias(RegisterRef RA, RegisterRef RB) const
Definition RDFRegisters.cpp:100
std::set< RegisterId > getAliasSet(RegisterRef RR) const
Definition RDFRegisters.cpp:104
bool less(RegisterRef A, RegisterRef B) const
Definition RDFRegisters.cpp:214
RegisterRef mapTo(RegisterRef RR, RegisterId R) const
Definition RDFRegisters.cpp:162
std::set< RegisterId > getUnits(RegisterRef RR) const
Definition RDFRegisters.cpp:126
ref_iterator(const RegisterAggr &RG, bool End)
Definition RDFRegisters.cpp:391
RegisterAggr & insert(RegisterRef RR)
Definition RDFRegisters.cpp:304
RegisterAggr(const PhysicalRegisterInfo &pri)
RegisterRef clearIn(RegisterRef RR) const
Definition RDFRegisters.cpp:351
RegisterAggr & clear(RegisterRef RR)
Definition RDFRegisters.cpp:332
RegisterRef makeRegRef() const
Definition RDFRegisters.cpp:355
RegisterAggr & intersect(RegisterRef RR)
Definition RDFRegisters.cpp:323
bool hasAliasOf(RegisterRef RR) const
Definition RDFRegisters.cpp:276
RegisterRef intersectWith(RegisterRef RR) const
Definition RDFRegisters.cpp:341
bool hasCoverOf(RegisterRef RR) const
Definition RDFRegisters.cpp:289
constexpr bool isReg() const
constexpr bool isMask() const
constexpr bool isUnit() const
constexpr MCRegister asMCReg() const