RISCVBaseInfo.cpp Source File (original) (raw)

22namespace llvm {

26namespace RISCVSysReg {

27#define GET_SysRegsList_IMPL

28#include "RISCVGenSearchableTables.inc"

29}

31namespace RISCVInsnOpcode {

32#define GET_RISCVOpcodesList_IMPL

33#include "RISCVGenSearchableTables.inc"

34}

36namespace RISCVABI {

40 bool IsRV64 = TT.isArch64Bit();

41 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];

45 << "'" << ABIName

46 << "' is not a recognized ABI for this target (ignoring target-abi)\n";

47 } else if (ABIName.starts_with("ilp32") && IsRV64) {

48 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "

49 "target-abi)\n";

51 } else if (ABIName.starts_with("lp64") && !IsRV64) {

52 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "

53 "target-abi)\n";

55 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&

59 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";

61 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&

65 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";

67 }

70 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&

71 FeatureBits[RISCV::FeatureStdExtD])

75 return TargetABI;

79 if (!ISAInfo)

81 return getTargetABI((*ISAInfo)->computeDefaultABI());

82}

95 return TargetABI;

96}

100

102

103

105

106}

107

108namespace RISCVFeatures {

109

111 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])

113 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])

115 if (FeatureBits[RISCV::Feature32Bit] &&

116 FeatureBits[RISCV::Feature64Bit])

118}

119

122 unsigned XLen = IsRV64 ? 64 : 32;

123 std::vectorstd::string FeatureVector;

124

126 if (FeatureBits[Feature.Value] &&

128 FeatureVector.push_back(std::string("+") + Feature.Key);

129 }

131}

132

133}

134

135

136#define GEN_UNCOMPRESS_INSTR

137#define GEN_COMPRESS_INSTR

138#include "RISCVGenCompressInstEmitter.inc"

139

142 return compressInst(OutInst, MI, STI);

143}

144

147 return uncompressInst(OutInst, MI, STI);

148}

149

150

152 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},

153 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},

154 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},

155 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},

156 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},

157 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},

158 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},

159 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},

160 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},

161 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},

162};

163

168 "Unexpected semantics");

169

170

172 return 1;

173

174

175 bool LosesInfo;

179 return -1;

180

182

183 if (Imm.extractBitsAsZExtValue(21, 0) != 0)

184 return -1;

185

186 bool Sign = Imm.extractBitsAsZExtValue(1, 31);

187 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);

188 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);

189

191 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||

192 EMI->second != Mantissa)

193 return -1;

194

195

196 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;

197

198

199 if (Sign) {

200 if (Entry == 16)

201 return 0;

202 return -1;

203 }

204

205 return Entry;

206}

207

209 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");

210

211

213 if (Imm == 0) {

214 Sign = 0b1;

215 Imm = 16;

216 }

217

220

221 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;

222 return bit_cast(I);

223}

224

226 OS << "{ra";

227 if (SlistEncode > 4) {

228 OS << ", s0";

229 if (SlistEncode == 15)

230 OS << "-s11";

231 else if (SlistEncode > 5 && SlistEncode <= 14)

232 OS << "-s" << (SlistEncode - 5);

233 }

234 OS << "}";

235}

236

237}

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)

const fltSemantics & getSemantics() const

APInt bitcastToAPInt() const

bool isSmallestNormalized() const

Class for arbitrary precision integers.

Tagged union holding either a T or a Error.

Container class for subtarget features.

Instances of this class represent a single low-level machine instruction.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

static bool isSupportedExtensionFeature(StringRef Ext)

static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)

Parse RISC-V ISA info from feature vector.

StringRef - Represent a constant reference to a string, i.e.

bool starts_with(StringRef Prefix) const

Check if this string starts with the given Prefix.

constexpr bool empty() const

empty - Check if the string is empty.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

Triple - Helper class for working with autoconf configuration names.

This class implements an extremely fast bulk output stream that can only output to a stream.

ABI getTargetABI(StringRef ABIName)

ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)

void validate(const Triple &TT, const FeatureBitset &FeatureBits)

llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)

int getLoadFPImm(APFloat FPImm)

getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.

float getFPImm(unsigned Imm)

bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)

bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)

void printRlist(unsigned SlistEncode, raw_ostream &OS)

This is an optimization pass for GlobalISel generic memory operations.

static constexpr std::pair< uint8_t, uint8_t > LoadFP32ImmArr[]

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]

static const fltSemantics & IEEEsingle() LLVM_READNONE

static constexpr roundingMode rmNearestTiesToEven

static const fltSemantics & IEEEdouble() LLVM_READNONE

static const fltSemantics & IEEEhalf() LLVM_READNONE

opStatus

IEEE-754R 7: Default exception handling.

Used to provide key value pairs for feature and CPU bit flags.