RISCVBaseInfo.cpp Source File (original) (raw)

22namespace llvm {

27#define GET_SysRegsList_IMPL

28#include "RISCVGenSearchableTables.inc"

29}

32#define GET_RISCVOpcodesList_IMPL

33#include "RISCVGenSearchableTables.inc"

34}

37using namespace RISCV;

38#define GET_RISCVVInversePseudosTable_IMPL

39#include "RISCVGenSearchableTables.inc"

40}

43#define GET_RISCVVSSEGTable_IMPL

44#define GET_RISCVVLSEGTable_IMPL

45#define GET_RISCVVLXSEGTable_IMPL

46#define GET_RISCVVSXSEGTable_IMPL

47#define GET_RISCVVLETable_IMPL

48#define GET_RISCVVSETable_IMPL

49#define GET_RISCVVLXTable_IMPL

50#define GET_RISCVVSXTable_IMPL

51#define GET_RISCVNDSVLNTable_IMPL

52#include "RISCVGenSearchableTables.inc"

53}

59 bool IsRV64 = TT.isArch64Bit();

60 bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];

64 << "'" << ABIName

65 << "' is not a recognized ABI for this target (ignoring target-abi)\n";

66 } else if (ABIName.starts_with("ilp32") && IsRV64) {

67 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "

68 "target-abi)\n";

70 } else if (ABIName.starts_with("lp64") && !IsRV64) {

71 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "

72 "target-abi)\n";

74 } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&

78 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";

80 } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&

84 << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";

86 }

89 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&

90 FeatureBits[RISCV::FeatureStdExtD])

94 return TargetABI;

98 if (!ISAInfo)

100 return getTargetABI((*ISAInfo)->computeDefaultABI());

101}

102

114 return TargetABI;

115}

116

117

118

119

121

122

124

125}

126

128

130 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])

132 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])

134 if (FeatureBits[RISCV::Feature32Bit] &&

135 FeatureBits[RISCV::Feature64Bit])

137}

138

141 unsigned XLen = IsRV64 ? 64 : 32;

142 std::vectorstd::string FeatureVector;

143

145 if (FeatureBits[Feature.Value] &&

147 FeatureVector.push_back(std::string("+") + Feature.Key);

148 }

150}

151

152}

153

154

155#define GEN_UNCOMPRESS_INSTR

156#define GEN_COMPRESS_INSTR

157#include "RISCVGenCompressInstEmitter.inc"

158

161 return compressInst(OutInst, MI, STI);

162}

163

166 return uncompressInst(OutInst, MI, STI);

167}

168

169

171 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},

172 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},

173 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},

174 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},

175 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},

176 {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},

177 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},

178 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},

179 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},

180 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},

181};

182

187 "Unexpected semantics");

188

189

191 return 1;

192

193

194 bool LosesInfo;

198 return -1;

199

201

202 if (Imm.extractBitsAsZExtValue(21, 0) != 0)

203 return -1;

204

205 bool Sign = Imm.extractBitsAsZExtValue(1, 31);

206 uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);

207 uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);

208

210 if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||

211 EMI->second != Mantissa)

212 return -1;

213

214

215 int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;

216

217

218 if (Sign) {

219 if (Entry == 16)

220 return 0;

221 return -1;

222 }

223

224 return Entry;

225}

226

228 assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");

229

230

232 if (Imm == 0) {

233 Sign = 0b1;

234 Imm = 16;

235 }

236

239

240 uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;

242}

243

247 OS << "{ra";

249 OS << ", s0";

251 OS << "-s11";

254 }

255 OS << "}";

256}

257

258}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static const fltSemantics & IEEEsingle()

static const fltSemantics & IEEEdouble()

static constexpr roundingMode rmNearestTiesToEven

static const fltSemantics & IEEEhalf()

opStatus

IEEE-754R 7: Default exception handling.

LLVM_ABI opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)

const fltSemantics & getSemantics() const

APInt bitcastToAPInt() const

bool isSmallestNormalized() const

Class for arbitrary precision integers.

Tagged union holding either a T or a Error.

Container class for subtarget features.

Instances of this class represent a single low-level machine instruction.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

static LLVM_ABI bool isSupportedExtensionFeature(StringRef Ext)

static LLVM_ABI llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatures(unsigned XLen, const std::vector< std::string > &Features)

Parse RISC-V ISA info from feature vector.

StringRef - Represent a constant reference to a string, i.e.

bool starts_with(StringRef Prefix) const

Check if this string starts with the given Prefix.

constexpr bool empty() const

empty - Check if the string is empty.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

Triple - Helper class for working with autoconf configuration names.

This class implements an extremely fast bulk output stream that can only output to a stream.

Definition RISCVBaseInfo.cpp:55

ABI getTargetABI(StringRef ABIName)

Definition RISCVBaseInfo.cpp:103

ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)

Definition RISCVBaseInfo.cpp:56

MCRegister getBPReg()

Definition RISCVBaseInfo.cpp:120

MCRegister getSCSPReg()

Definition RISCVBaseInfo.cpp:123

Definition RISCVBaseInfo.cpp:127

void validate(const Triple &TT, const FeatureBitset &FeatureBits)

Definition RISCVBaseInfo.cpp:129

llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)

Definition RISCVBaseInfo.cpp:140

Definition RISCVBaseInfo.cpp:31

int getLoadFPImm(APFloat FPImm)

getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.

Definition RISCVBaseInfo.cpp:183

float getFPImm(unsigned Imm)

Definition RISCVBaseInfo.cpp:227

bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)

Definition RISCVBaseInfo.cpp:164

bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)

Definition RISCVBaseInfo.cpp:159

Definition RISCVBaseInfo.cpp:26

Definition RISCVBaseInfo.cpp:36

void printRegList(unsigned RlistEncode, raw_ostream &OS)

Definition RISCVBaseInfo.cpp:244

This is an optimization pass for GlobalISel generic memory operations.

static constexpr std::pair< uint8_t, uint8_t > LoadFP32ImmArr[]

Definition RISCVBaseInfo.cpp:170

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

To bit_cast(const From &from) noexcept

const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]

Definition RISCVBaseInfo.cpp:24

LLVM_ABI void reportFatalUsageError(Error Err)

Report a fatal error that does not indicate a bug in LLVM.

Used to provide key value pairs for feature and CPU bit flags.