RISCVDisassembler.cpp Source File (original) (raw)

28using namespace llvm;

31#define DEBUG_TYPE "riscv-disassembler"

35namespace {

37 std::unique_ptr const MCII;

39public:

48private:

59};

60}

65 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());

66}

86 if (RegNo >= 32 || (IsRVE && RegNo >= 16))

92}

99 if (RegNo >= 32 || (IsRVE && RegNo >= 16))

101

105}

106

111

112 if (RegNo >= 32 || (IsRVE && RegNo >= 16))

114

118}

119

124 if (Reg != RISCV::X1 && Reg != RISCV::X5)

126

129}

130

134 if (RegNo >= 32)

136

140}

141

145 if (RegNo >= 32)

147

151}

152

156 if (RegNo >= 8) {

158 }

162}

163

167 if (RegNo >= 32)

169

173}

174

178 if (RegNo >= 8) {

180 }

184}

185

189 if (RegNo >= 32)

191

195}

196

202

208

216

222

226 if (RegNo == 0)

228

230}

231

235 if (RegNo == 2)

237

239}

240

244 if (RegNo == 31) {

246 }

247

249}

250

254 if (RegNo >= 8)

256

260}

261

265 if (RegNo >= 32 || RegNo % 2)

267

268 const RISCVDisassembler *Dis =

269 static_cast<const RISCVDisassembler *>(Decoder);

270 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();

272 RISCV::X0 + RegNo, RISCV::sub_gpr_even,

273 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);

276}

277

281 if (RegNo == 0)

283

285}

286

290 if (RegNo >= 8 || RegNo % 2)

292

293 const RISCVDisassembler *Dis =

294 static_cast<const RISCVDisassembler *>(Decoder);

295 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();

297 RISCV::X8 + RegNo, RISCV::sub_gpr_even,

298 &RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID]);

301}

302

305 const void *Decoder) {

306 if (RegNo >= 8)

308

309 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);

312}

313

317 if (RegNo >= 32)

319

323}

324

328 if (RegNo >= 32 || RegNo % 2)

330

331 const RISCVDisassembler *Dis =

332 static_cast<const RISCVDisassembler *>(Decoder);

333 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();

336 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);

337

340}

341

345 if (RegNo >= 32 || RegNo % 4)

347

348 const RISCVDisassembler *Dis =

349 static_cast<const RISCVDisassembler *>(Decoder);

350 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();

353 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);

354

357}

358

362 if (RegNo >= 32 || RegNo % 8)

364

365 const RISCVDisassembler *Dis =

366 static_cast<const RISCVDisassembler *>(Decoder);

367 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();

370 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);

371

374}

375

385

389 if (RegNo > 15)

391

395}

396

400 if (RegNo > 15 || RegNo % 2)

402

406}

407

411 if (RegNo > 15 || RegNo % 4)

413

417}

418

422 if (RegNo >= 2)

424

425 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;

426

429}

430

436

442

443template

445 int64_t Address,

450}

451

452template <unsigned Width, unsigned LowerBound>

454 int64_t Address,

457

458 if (Imm < LowerBound)

460

463}

464

465template <unsigned Width, unsigned LowerBound>

467 int64_t Address,

470

471 if ((Imm + 1) < LowerBound)

473

476}

477

479 int64_t Address,

482 const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};

485}

486

488 int64_t Address,

491

495

498}

499

500template

502 int64_t Address,

504 if (Imm == 0)

507}

508

516

517template

519 int64_t Address,

524}

525

527 int64_t Address,

532}

533

534template

536 int64_t Address,

539

542}

543

544template

546 int64_t Address,

548 if (Imm == 0)

551}

552

553template <unsigned T, unsigned N>

555 int64_t Address,

558

559

560

563}

564

566 int64_t Address,

569 if (Imm == 0)

574}

575

585

595

605

613

614#include "RISCVGenDisassemblerTables.inc"

615

616namespace {

617

618struct DecoderListEntry {

619 const uint8_t *Table;

620 FeatureBitset ContainedFeatures;

621 const char *Desc;

622

623 bool haveContainedFeatures(const FeatureBitset &ActiveFeatures) const {

624 return ContainedFeatures.none() ||

625 (ContainedFeatures & ActiveFeatures).any();

626 }

627};

628

629}

630

632 RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,

633 RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,

634 RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,

635 RISCV::FeatureVendorXCVbi};

636

638 RISCV::FeatureVendorXRivosVisni,

639 RISCV::FeatureVendorXRivosVizip,

640};

641

643 RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,

644 RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,

645 RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,

646 RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,

647 RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,

648 RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,

649 RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,

650 RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,

651 RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,

652};

653

655 RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,

656 RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,

657 RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase,

658 RISCV::FeatureVendorXSfvfexpa, RISCV::FeatureVendorXSfvfexpa64e,

659 RISCV::FeatureVendorXSfvfbfexp16e, RISCV::FeatureVendorXSfvfexp16e,

660 RISCV::FeatureVendorXSfvfexp32e};

662 RISCV::FeatureVendorXSiFivecdiscarddlone,

663 RISCV::FeatureVendorXSiFivecflushdlone,

664};

665

667 RISCV::FeatureVendorXMIPSLSP,

668 RISCV::FeatureVendorXMIPSCMov,

669 RISCV::FeatureVendorXMIPSCBOP,

670 RISCV::FeatureVendorXMIPSEXECTL,

671};

672

674 RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,

675 RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,

676 RISCV::FeatureVendorXTHeadCmo, RISCV::FeatureVendorXTHeadFMemIdx,

677 RISCV::FeatureVendorXTHeadMac, RISCV::FeatureVendorXTHeadMemIdx,

678 RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,

679 RISCV::FeatureVendorXTHeadVdot};

680

682 RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,

683 RISCV::FeatureVendorXAndesVBFHCvt, RISCV::FeatureVendorXAndesVSIntH,

684 RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,

685 RISCV::FeatureVendorXAndesVDot};

686

688

690

691 {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},

693 {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},

694 {DecoderTableXVentana32,

695 {RISCV::FeatureVendorXVentanaCondOps},

696 "XVentanaCondOps"},

697 {DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},

698 {DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},

699 {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},

700 {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},

701 {DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},

702 {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},

703 {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},

704

705 {DecoderTable32, {}, "standard 32-bit instructions"},

706 {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},

707 {DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},

708 {DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},

709};

710

711namespace {

712

713template <> constexpr uint32_t InsnBitWidth<uint16_t> = 16;

714template <> constexpr uint32_t InsnBitWidth<uint32_t> = 32;

715

716template <> constexpr uint32_t InsnBitWidth<uint64_t> = 48;

717}

718

723 if (Bytes.size() < 4) {

726 }

728

730

731 for (const DecoderListEntry &Entry : DecoderList32) {

732 if ( Entry .haveContainedFeatures(STI.getFeatureBits()))

733 continue;

734

737 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);

739 continue;

740

742 }

743

745}

746

748

749 {DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},

750 {DecoderTableXqccmp16,

751 {RISCV::FeatureVendorXqccmp},

752 "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},

753 {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},

754

755

756 {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},

757 {DecoderTable16, {}, "standard 16-bit instructions"},

758 {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},

759

760 {DecoderTableZcOverlap16,

761 {},

762 "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)"},

763};

764

765DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,

766 ArrayRef<uint8_t> Bytes,

768 raw_ostream &CS) const {

769 if (Bytes.size() < 2) {

772 }

774

776

777 for (const DecoderListEntry &Entry : DecoderList16) {

778 if ( Entry .haveContainedFeatures(STI.getFeatureBits()))

779 continue;

780

783 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);

786 }

787

789}

790

794

795DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,

796 ArrayRef<uint8_t> Bytes,

798 raw_ostream &CS) const {

799 if (Bytes.size() < 6) {

802 }

804

805 uint64_t Insn = 0;

806 for (size_t i = Size; i-- != 0;)

807 Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);

808

809 for (const DecoderListEntry &Entry : DecoderList48) {

810 if ( Entry .haveContainedFeatures(STI.getFeatureBits()))

811 continue;

812

815 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);

817 continue;

818

820 }

821

823}

824

825DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

826 ArrayRef<uint8_t> Bytes,

828 raw_ostream &CS) const {

829 CommentStream = &CS;

830

831 if ((Bytes[0] & 0b11) != 0b11)

832 return getInstruction16(MI, Size, Bytes, Address, CS);

833

834

835

836 if ((Bytes[0] & 0b1'1100) != 0b1'1100)

837 return getInstruction32(MI, Size, Bytes, Address, CS);

838

839

840 if ((Bytes[0] & 0b11'1111) == 0b01'1111) {

841 return getInstruction48(MI, Size, Bytes, Address, CS);

842 }

843

844

845 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {

846 Size = Bytes.size() >= 8 ? 8 : 0;

848 }

849

850

851 if (Bytes.size() < 2) {

854 }

855

856

857

858 unsigned nnn = (Bytes[1] >> 4) & 0b111;

859 if (nnn != 0b111) {

860 Size = 10 + (nnn * 2);

864 }

865

866

869}

MCDisassembler::DecodeStatus DecodeStatus

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define LLVM_EXTERNAL_VISIBILITY

static constexpr FeatureBitset XqciFeatureGroup

Definition RISCVDisassembler.cpp:642

static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:478

static constexpr FeatureBitset XSMTGroup

Definition RISCVDisassembler.cpp:687

static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:487

static constexpr FeatureBitset XCVFeatureGroup

Definition RISCVDisassembler.cpp:631

static constexpr DecoderListEntry DecoderList48[]

Definition RISCVDisassembler.cpp:791

static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:535

static constexpr DecoderListEntry DecoderList16[]

Definition RISCVDisassembler.cpp:747

static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:120

static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:241

static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:251

static DecodeStatus decodeImmFourOperand(MCInst &Inst, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:437

static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:164

static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:510

static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:586

static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition RISCVDisassembler.cpp:62

static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:94

static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:397

static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:186

static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:554

static constexpr FeatureBitset XSfVectorGroup

Definition RISCVDisassembler.cpp:654

static constexpr DecoderListEntry DecoderList32[]

Definition RISCVDisassembler.cpp:689

static DecodeStatus DecodeGPRX5RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:217

static DecodeStatus decodeImmThreeOperand(MCInst &Inst, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:431

static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:606

static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:153

static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:518

static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:565

static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:596

static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:444

static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:142

static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:359

static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:342

static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:232

static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:314

static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:325

static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:262

static DecodeStatus decodeImmZibiOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:526

static DecodeStatus DecodeSPRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:203

static constexpr FeatureBitset XMIPSGroup

Definition RISCVDisassembler.cpp:666

static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:545

static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:279

static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:376

static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:386

static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:175

static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:107

static constexpr FeatureBitset XAndesGroup

Definition RISCVDisassembler.cpp:681

static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:408

static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:223

static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:576

static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:197

static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const void *Decoder)

Definition RISCVDisassembler.cpp:303

static constexpr FeatureBitset XTHeadGroup

Definition RISCVDisassembler.cpp:673

static constexpr FeatureBitset XRivosFeatureGroup

Definition RISCVDisassembler.cpp:637

static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:466

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()

Definition RISCVDisassembler.cpp:69

static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:131

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:81

static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:419

static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:501

static constexpr FeatureBitset XSfSystemGroup

Definition RISCVDisassembler.cpp:661

static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:453

static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition RISCVDisassembler.cpp:287

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Container class for subtarget features.

Context object for machine code objects.

Superclass for all disassemblers.

const MCSubtargetInfo & getSubtargetInfo() const

DecodeStatus

Ternary decode status.

Instances of this class represent a single low-level machine instruction.

void addOperand(const MCOperand Op)

Interface to description of machine instruction set.

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const

Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

Target - Wrapper for Target specific information.

This class implements an extremely fast bulk output stream that can only output to a stream.

constexpr bool any(E Val)

static bool isValidRoundingMode(unsigned Mode)

uint16_t read16le(const void *P)

uint32_t read32le(const void *P)

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheRISCV32Target()

Target & getTheRISCV64beTarget()

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

Target & getTheRISCV64Target()

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

Target & getTheRISCV32beTarget()

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.