RISCVISelDAGToDAG.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H

14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H

23namespace llvm {

27public:

46 std::vector &OutOps) override;

58 template

68 template <unsigned MaxShift, unsigned Bits>

80 SDValue X, unsigned Msb, unsigned Lsb);

82 SDValue X, unsigned Msb, unsigned Lsb);

100

109

114

119

123

126 const unsigned Depth = 0) const;

130

132

134

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154

156 const SDLoc &DL, unsigned CurOp,

157 bool IsMasked, bool IsStridedOrIndexed,

159 bool IsLoad = false, MVT *IndexVT = nullptr);

160

166

169

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172

173

174

176 switch (CC) {

177 default:

191 }

192 }

193

194

195#define GET_DAGISEL_DECL

196#include "RISCVGenDAGISel.inc"

197

198private:

199 bool doPeepholeSExtW(SDNode *Node);

200 bool doPeepholeMaskedRVV(MachineSDNode *Node);

201 bool doPeepholeNoRegPassThru();

202 bool performCombineVMergeAndVOps(SDNode *N);

203 bool selectImm64IfCheaper(int64_t Imm, int64_t OrigImm, SDValue N,

205};

206

213

214}

215

216#endif

AMDGPU Register Bank Select

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

static char ID

Definition RISCVISelDAGToDAG.h:209

RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)

bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)

RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with ...

bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val)

bool selectNegImm(SDValue N, SDValue &Val)

bool selectSHXADD_UWOp(SDValue N, SDValue &Val)

Definition RISCVISelDAGToDAG.h:116

bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)

bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.

bool areOffsetsWithinAlignment(SDValue Addr, Align Alignment)

bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const

bool selectVSplatUimmBits(SDValue N, SDValue &Val)

Definition RISCVISelDAGToDAG.h:138

bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset)

Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset should be all zeros.

bool selectZExtImm32(SDValue N, SDValue &Val)

bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)

Definition RISCVISelDAGToDAG.h:86

bool SelectAddrRegZextRegScale(SDValue Addr, unsigned MaxShiftAmount, unsigned Bits, SDValue &Base, SDValue &Index, SDValue &Scale)

bool SelectAddrRegReg(SDValue Addr, SDValue &Base, SDValue &Offset)

bool selectSETEQ(SDValue N, SDValue &Val)

Definition RISCVISelDAGToDAG.h:97

void selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered)

RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)

Definition RISCVISelDAGToDAG.h:30

void selectVLSEGFF(SDNode *Node, unsigned NF, bool IsMasked)

bool selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal)

bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2)

void selectSF_VC_X_SE(SDNode *Node)

bool orDisjoint(const SDNode *Node) const

bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal)

bool hasAllHUsers(SDNode *Node) const

Definition RISCVISelDAGToDAG.h:128

bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...

bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)

bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)

bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)

bool tryUnsignedBitfieldInsertInZero(SDNode *Node, const SDLoc &DL, MVT VT, SDValue X, unsigned Msb, unsigned Lsb)

bool hasAllWUsers(SDNode *Node) const

Definition RISCVISelDAGToDAG.h:129

void PreprocessISelDAG() override

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...

bool runOnMachineFunction(MachineFunction &MF) override

Definition RISCVISelDAGToDAG.h:34

bool selectInvLogicImm(SDValue N, SDValue &Val)

bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)

bool selectSExtBits(SDValue N, SDValue &Val)

Definition RISCVISelDAGToDAG.h:102

RISCVDAGToDAGISel()=delete

void selectXSfmmVSET(SDNode *Node)

bool trySignedBitfieldInsertInSign(SDNode *Node)

bool selectVSplat(SDValue N, SDValue &SplatVal)

void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)

void PostprocessISelDAG() override

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset)

Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.

bool selectScalarFPAsInt(SDValue N, SDValue &Imm)

bool hasAllBUsers(SDNode *Node) const

Definition RISCVISelDAGToDAG.h:127

void selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided)

bool tryShrinkShlLogicImm(SDNode *Node)

bool selectSETNE(SDValue N, SDValue &Val)

Definition RISCVISelDAGToDAG.h:94

bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)

Definition RISCVISelDAGToDAG.h:59

void selectVSETVLI(SDNode *Node)

bool selectShiftMask32(SDValue N, SDValue &ShAmt)

Definition RISCVISelDAGToDAG.h:89

bool selectVLOp(SDValue N, SDValue &VL)

bool trySignedBitfieldExtract(SDNode *Node)

bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)

bool selectRVVSimm5(SDValue N, SDValue &Imm)

Definition RISCVISelDAGToDAG.h:151

void selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided)

bool selectVSplatImm64Neg(SDValue N, SDValue &SplatVal)

bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)

bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)

Definition RISCVISelDAGToDAG.h:69

bool selectSHXADDOp(SDValue N, SDValue &Val)

Definition RISCVISelDAGToDAG.h:111

bool tryUnsignedBitfieldExtract(SDNode *Node, const SDLoc &DL, MVT VT, SDValue X, unsigned Msb, unsigned Lsb)

bool selectZExtBits(SDValue N, SDValue &Val)

Definition RISCVISelDAGToDAG.h:106

void selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered)

bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)

bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD.

bool tryIndexedLoad(SDNode *Node)

bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)

static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)

Definition RISCVISelDAGToDAG.h:175

bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal)

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SelectionDAGISelLegacy(char &ID, std::unique_ptr< SelectionDAGISel > S)

SelectionDAGISel(TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default)

virtual bool runOnMachineFunction(MachineFunction &mf)

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Primary interface to the complete machine description for the target machine.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

This is an optimization pass for GlobalISel generic memory operations.

CodeGenOptLevel

Code generation optimization level.

DWARFExpression::Operation Op

This struct is a compact representation of a valid (non-zero power of two) alignment.