LLVM: lib/Target/RISCV/RISCVInstrInfo.cpp File Reference (original) (raw)

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Macros
#define GEN_CHECK_COMPRESS_INSTR
#define GET_INSTRINFO_CTOR_DTOR
#define GET_INSTRINFO_NAMED_OPS
#define DEBUG_TYPE "riscv-instr-info"
#define GET_RISCVVPseudosTable_IMPL
#define GET_RISCVMaskedPseudosTable_IMPL
#define GET_INSTRINFO_HELPERS
#define OPCODE_LMUL_CASE(OPC)
#define OPCODE_LMUL_MASK_CASE(OPC)
#define RVV_OPC_LMUL_CASE(OPC, INV)
#define RVV_OPC_LMUL_MASK_CASE(OPC, INV)
#define CASE_OPERAND_UIMM(NUM)
#define CASE_OPERAND_SIMM(NUM)
#define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL)
#define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)
#define CASE_RVV_OPCODE_LMUL(OP, LMUL)
#define CASE_RVV_OPCODE_UNMASK_WIDEN(OP)
#define CASE_RVV_OPCODE_UNMASK(OP)
#define CASE_RVV_OPCODE_MASK_WIDEN(OP)
#define CASE_RVV_OPCODE_MASK(OP)
#define CASE_RVV_OPCODE_WIDEN(OP)
#define CASE_RVV_OPCODE(OP)
#define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL)
#define CASE_VMA_OPCODE_LMULS(OP, TYPE)
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW)
#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)
#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)
#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE, SEW)
#define CASE_VFMA_OPCODE_VV(OP)
#define CASE_VFMA_SPLATS(OP)
#define CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)
#define CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)
#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)
#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP)
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)
#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)
#define CASE_WIDEOP_OPCODE_LMULS(OP)
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP)
#define CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW)
#define CASE_FP_WIDEOP_OPCODE_LMULS(OP)
#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW)
#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(OP)
#define CASE_FP_WIDEOP_OPCODE_LMULS_ALT(OP)
#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT(OP)
Functions
STATISTIC (NumVRegSpilled, "Number of registers within vector register groups spilled")
STATISTIC (NumVRegReloaded, "Number of registers within vector register groups reloaded")
static std::optional< unsigned > getLMULForRVVWholeLoadStore (unsigned Opcode)
static bool forwardCopyWillClobberTuple (unsigned DstReg, unsigned SrcReg, unsigned NumRegs)
static bool isConvertibleToVMV_V_V (const RISCVSubtarget &STI, const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI, MachineBasicBlock::const_iterator &DefMBBI, RISCVVType::VLMUL LMul)
std::optional< unsigned > getFoldedOpcode (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, const RISCVSubtarget &ST)
static void parseCondBranch (MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
static unsigned getInverseXqcicmOpcode (unsigned Opcode)
static bool isLoadImm (const MachineInstr *MI, int64_t &Imm)
unsigned getPredicatedOpcode (unsigned Opcode)
static MachineInstr * canFoldAsPredicatedOp (Register Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII, const RISCVSubtarget &STI)
Identify instructions that can be folded into a CCMOV instruction, and return the defining instruction.
static bool isFADD (unsigned Opc)
static bool isFSUB (unsigned Opc)
static bool isFMUL (unsigned Opc)
static bool canCombineFPFusedMultiply (const MachineInstr &Root, const MachineOperand &MO, bool DoRegPressureReduce)
static bool getFPFusedMultiplyPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)
static bool getFPPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce)
static const MachineInstr * canCombine (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned CombineOpc)
Utility routine that checks if.
static bool canCombineShiftIntoShXAdd (const MachineBasicBlock &MBB, const MachineOperand &MO, unsigned OuterShiftAmt)
Utility routine that checks if.
static unsigned getSHXADDShiftAmount (unsigned Opc)
static unsigned getSHXADDUWShiftAmount (unsigned Opc)
static bool getSHXADDPatterns (const MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static unsigned getFPFusedMultiplyOpcode (unsigned RootOpc, unsigned Pattern)
static unsigned getAddendOperandIdx (unsigned Pattern)
static void combineFPFusedMultiply (MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs)
static void genShXAddAddShift (MachineInstr &Root, unsigned AddOpIdx, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg)
static bool memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
static bool isCandidatePatchable (const MachineBasicBlock &MBB)
static bool isMIReadsReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, MCRegister RegNo)
static bool isMIModifiesReg (const MachineInstr &MI, const TargetRegisterInfo *TRI, MCRegister RegNo)
static bool cannotInsertTailCall (const MachineBasicBlock &MBB)
static bool analyzeCandidate (outliner::Candidate &C)
static std::optional< int64_t > getEffectiveImm (const MachineOperand &MO)
Variables
static cl::opt< bool > PreferWholeRegisterMove ("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers."))
static cl::opt< MachineTraceStrategy > ForceMachineCombinerStrategy ("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy.")))

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON ( OP,
LMUL,
SEW )

Value:

case RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED: \

NewOpc = RISCV::PseudoV##OP##_##LMUL##_##SEW; \

break;

Definition at line 4558 of file RISCVInstrInfo.cpp.

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS ( OP )

Value:

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E32) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E32) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E32) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E32) \

#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW)

unsigned M1(unsigned Val)

Definition at line 4563 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT

#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT ( OP )

Value:

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16) \

CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16)

Definition at line 4581 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_FP_WIDEOP_OPCODE_COMMON

#define CASE_FP_WIDEOP_OPCODE_COMMON ( OP,
LMUL,
SEW )

◆ CASE_FP_WIDEOP_OPCODE_LMULS

#define CASE_FP_WIDEOP_OPCODE_LMULS ( OP )

Value:

CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16): \

case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16): \

case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E32): \

case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16): \

case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E32): \

case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16): \

case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E32) \

#define CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW)

Definition at line 4547 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::convertToThreeAddress().

◆ CASE_FP_WIDEOP_OPCODE_LMULS_ALT

#define CASE_FP_WIDEOP_OPCODE_LMULS_ALT ( OP )

◆ CASE_OPERAND_SIMM

#define CASE_OPERAND_SIMM ( NUM )

◆ CASE_OPERAND_UIMM

#define CASE_OPERAND_UIMM ( NUM )

◆ CASE_RVV_OPCODE

#define CASE_RVV_OPCODE ( OP )

◆ CASE_RVV_OPCODE_LMUL

#define CASE_RVV_OPCODE_LMUL ( OP,
LMUL )

Value:

case CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)

#define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL)

#define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)

Definition at line 3805 of file RISCVInstrInfo.cpp.

◆ CASE_RVV_OPCODE_MASK

#define CASE_RVV_OPCODE_MASK ( OP )

◆ CASE_RVV_OPCODE_MASK_LMUL

#define CASE_RVV_OPCODE_MASK_LMUL ( OP,
LMUL )

◆ CASE_RVV_OPCODE_MASK_WIDEN

#define CASE_RVV_OPCODE_MASK_WIDEN ( OP )

◆ CASE_RVV_OPCODE_UNMASK

#define CASE_RVV_OPCODE_UNMASK ( OP )

◆ CASE_RVV_OPCODE_UNMASK_LMUL

#define CASE_RVV_OPCODE_UNMASK_LMUL ( OP,
LMUL )

◆ CASE_RVV_OPCODE_UNMASK_WIDEN

#define CASE_RVV_OPCODE_UNMASK_WIDEN ( OP )

◆ CASE_RVV_OPCODE_WIDEN

#define CASE_RVV_OPCODE_WIDEN ( OP )

◆ CASE_VFMA_CHANGE_OPCODE_COMMON

#define CASE_VFMA_CHANGE_OPCODE_COMMON ( OLDOP,
NEWOP,
TYPE,
LMUL,
SEW )

Value:

case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_##SEW: \

Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_##SEW; \

break;

Definition at line 4084 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_M1

#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1 ( OLDOP,
NEWOP,
TYPE,
SEW )

Value:

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1, SEW) \

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2, SEW) \

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4, SEW) \

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8, SEW)

#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW)

Definition at line 4089 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2 ( OLDOP,
NEWOP,
TYPE,
SEW )

Value:

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2, SEW) \

CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)

Definition at line 4095 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 ( OLDOP,
NEWOP,
TYPE,
SEW )

Value:

CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW) \

CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)

Definition at line 4099 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_CHANGE_OPCODE_SPLATS

#define CASE_VFMA_CHANGE_OPCODE_SPLATS ( OLDOP,
NEWOP )

Value:

CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16, E16) \

CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP##_ALT, NEWOP##_ALT, VFPR16, E16) \

CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32, E32) \

CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64, E64)

#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW)

Definition at line 4109 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl().

◆ CASE_VFMA_CHANGE_OPCODE_VV

#define CASE_VFMA_CHANGE_OPCODE_VV ( OLDOP,
NEWOP )

Value:

CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16) \

CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP##_ALT, NEWOP##_ALT, VV, E16) \

CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \

CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)

Definition at line 4103 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl().

◆ CASE_VFMA_OPCODE_COMMON

#define CASE_VFMA_OPCODE_COMMON ( OP,
TYPE,
LMUL,
SEW )

◆ CASE_VFMA_OPCODE_LMULS_M1

#define CASE_VFMA_OPCODE_LMULS_M1 ( OP,
TYPE,
SEW )

Value:

CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1, SEW): \

case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2, SEW): \

case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4, SEW): \

case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8, SEW)

#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW)

Definition at line 3859 of file RISCVInstrInfo.cpp.

◆ CASE_VFMA_OPCODE_LMULS_MF2

#define CASE_VFMA_OPCODE_LMULS_MF2 ( OP,
TYPE,
SEW )

◆ CASE_VFMA_OPCODE_LMULS_MF4

#define CASE_VFMA_OPCODE_LMULS_MF4 ( OP,
TYPE,
SEW )

◆ CASE_VFMA_OPCODE_VV

#define CASE_VFMA_OPCODE_VV ( OP )

Value:

CASE_VFMA_OPCODE_LMULS_MF4(OP, VV, E16): \

case CASE_VFMA_OPCODE_LMULS_MF4(OP##_ALT, VV, E16): \

case CASE_VFMA_OPCODE_LMULS_MF2(OP, VV, E32): \

case CASE_VFMA_OPCODE_LMULS_M1(OP, VV, E64)

#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE, SEW)

Definition at line 3873 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl(), and llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_VFMA_SPLATS

#define CASE_VFMA_SPLATS ( OP )

◆ CASE_VMA_CHANGE_OPCODE_COMMON

#define CASE_VMA_CHANGE_OPCODE_COMMON ( OLDOP,
NEWOP,
TYPE,
LMUL )

Value:

case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \

Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \

break;

Definition at line 4069 of file RISCVInstrInfo.cpp.

◆ CASE_VMA_CHANGE_OPCODE_LMULS

#define CASE_VMA_CHANGE_OPCODE_LMULS ( OLDOP,
NEWOP,
TYPE )

Value:

CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \

CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \

CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \

CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \

CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \

CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \

CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)

#define CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)

Definition at line 4074 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl().

◆ CASE_VMA_OPCODE_COMMON

#define CASE_VMA_OPCODE_COMMON ( OP,
TYPE,
LMUL )

◆ CASE_VMA_OPCODE_LMULS

#define CASE_VMA_OPCODE_LMULS ( OP,
TYPE )

Value:

CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8): \

case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4): \

case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2): \

case CASE_VMA_OPCODE_COMMON(OP, TYPE, M1): \

case CASE_VMA_OPCODE_COMMON(OP, TYPE, M2): \

case CASE_VMA_OPCODE_COMMON(OP, TYPE, M4): \

case CASE_VMA_OPCODE_COMMON(OP, TYPE, M8)

#define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL)

Definition at line 3846 of file RISCVInstrInfo.cpp.

Referenced by llvm::RISCVInstrInfo::commuteInstructionImpl(), and llvm::RISCVInstrInfo::findCommutedOpIndices().

◆ CASE_WIDEOP_CHANGE_OPCODE_COMMON

#define CASE_WIDEOP_CHANGE_OPCODE_COMMON ( OP,
LMUL )

Value:

case RISCV::PseudoV##OP##_##LMUL##_TIED: \

NewOpc = RISCV::PseudoV##OP##_##LMUL; \

break;

Definition at line 4530 of file RISCVInstrInfo.cpp.

◆ CASE_WIDEOP_CHANGE_OPCODE_LMULS

#define CASE_WIDEOP_CHANGE_OPCODE_LMULS ( OP )

◆ CASE_WIDEOP_OPCODE_COMMON

#define CASE_WIDEOP_OPCODE_COMMON ( OP,
LMUL )

◆ CASE_WIDEOP_OPCODE_LMULS

#define CASE_WIDEOP_OPCODE_LMULS ( OP )

◆ DEBUG_TYPE

#define DEBUG_TYPE "riscv-instr-info"

◆ GEN_CHECK_COMPRESS_INSTR

#define GEN_CHECK_COMPRESS_INSTR

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

◆ GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

◆ GET_RISCVMaskedPseudosTable_IMPL

#define GET_RISCVMaskedPseudosTable_IMPL

◆ GET_RISCVVPseudosTable_IMPL

#define GET_RISCVVPseudosTable_IMPL

◆ OPCODE_LMUL_CASE

#define OPCODE_LMUL_CASE ( OPC )

Value:

case RISCV::OPC##_M1: \

case RISCV::OPC##_M2: \

case RISCV::OPC##_M4: \

case RISCV::OPC##_M8: \

case RISCV::OPC##_MF2: \

case RISCV::OPC##_MF4: \

case RISCV::OPC##_MF8

◆ OPCODE_LMUL_MASK_CASE

#define OPCODE_LMUL_MASK_CASE ( OPC )

Value:

case RISCV::OPC##_M1_MASK: \

case RISCV::OPC##_M2_MASK: \

case RISCV::OPC##_M4_MASK: \

case RISCV::OPC##_M8_MASK: \

case RISCV::OPC##_MF2_MASK: \

case RISCV::OPC##_MF4_MASK: \

case RISCV::OPC##_MF8_MASK

◆ RVV_OPC_LMUL_CASE

#define RVV_OPC_LMUL_CASE ( OPC,
INV )

Value:

case RISCV::OPC##_M1: \

return RISCV::INV##_M1; \

case RISCV::OPC##_M2: \

return RISCV::INV##_M2; \

case RISCV::OPC##_M4: \

return RISCV::INV##_M4; \

case RISCV::OPC##_M8: \

return RISCV::INV##_M8; \

case RISCV::OPC##_MF2: \

return RISCV::INV##_MF2; \

case RISCV::OPC##_MF4: \

return RISCV::INV##_MF4; \

case RISCV::OPC##_MF8: \

return RISCV::INV##_MF8

Referenced by llvm::RISCVInstrInfo::getInverseOpcode().

◆ RVV_OPC_LMUL_MASK_CASE

#define RVV_OPC_LMUL_MASK_CASE ( OPC,
INV )

Value:

case RISCV::OPC##_M1_MASK: \

return RISCV::INV##_M1_MASK; \

case RISCV::OPC##_M2_MASK: \

return RISCV::INV##_M2_MASK; \

case RISCV::OPC##_M4_MASK: \

return RISCV::INV##_M4_MASK; \

case RISCV::OPC##_M8_MASK: \

return RISCV::INV##_M8_MASK; \

case RISCV::OPC##_MF2_MASK: \

return RISCV::INV##_MF2_MASK; \

case RISCV::OPC##_MF4_MASK: \

return RISCV::INV##_MF4_MASK; \

case RISCV::OPC##_MF8_MASK: \

return RISCV::INV##_MF8_MASK

Referenced by llvm::RISCVInstrInfo::getInverseOpcode().

◆ MachineOutlinerConstructionID

◆ analyzeCandidate()

◆ canCombine()

◆ canCombineFPFusedMultiply()

Definition at line 2507 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCV::hasEqualFRM(), isFMUL(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MI, and MRI.

Referenced by getFPFusedMultiplyPatterns().

◆ canCombineShiftIntoShXAdd()

◆ canFoldAsPredicatedOp()

◆ cannotInsertTailCall()

◆ combineFPFusedMultiply()

Definition at line 2718 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), getAddendOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getFlags(), getFPFusedMultiplyOpcode(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::DILocation::getMergedLocation(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

Referenced by llvm::RISCVInstrInfo::genAlternativeCodeSequence().

◆ forwardCopyWillClobberTuple()

◆ genShXAddAddShift()

Definition at line 2764 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getSHXADDShiftAmount(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::RegState::Kill, llvm_unreachable, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), TII, X, and Y.

Referenced by llvm::RISCVInstrInfo::genAlternativeCodeSequence().

◆ getAddendOperandIdx()

◆ getEffectiveImm()

◆ getFoldedOpcode()

◆ getFPFusedMultiplyOpcode()

◆ getFPFusedMultiplyPatterns()

Definition at line 2534 of file RISCVInstrInfo.cpp.

References canCombineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isFADD(), isFSUB(), Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by getFPPatterns().

◆ getFPPatterns()

◆ getInverseXqcicmOpcode()

◆ getLMULForRVVWholeLoadStore()

◆ getPredicatedOpcode()

◆ getSHXADDPatterns()

Definition at line 2632 of file RISCVInstrInfo.cpp.

References canCombine(), canCombineShiftIntoShXAdd(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), getSHXADDShiftAmount(), MBB, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SHXADD_ADD_SLLI_OP1, and llvm::SHXADD_ADD_SLLI_OP2.

Referenced by llvm::RISCVInstrInfo::getMachineCombinerPatterns().

◆ getSHXADDShiftAmount()

◆ getSHXADDUWShiftAmount()

◆ isCandidatePatchable()

◆ isConvertibleToVMV_V_V()

Definition at line 257 of file RISCVInstrInfo.cpp.

References assert(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::RISCVVType::getSEW(), llvm::RISCVVType::getVLMUL(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVLOp(), llvm::RISCVII::isRVVWideningReduction(), llvm::RISCVVType::isTailAgnostic(), MBB, MBBI, PreferWholeRegisterMove, and TRI.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector().

◆ isFADD()

◆ isFMUL()

◆ isFSUB()

◆ isLoadImm()

◆ isMIModifiesReg()

◆ isMIReadsReg()

◆ memOpsHaveSameBasePtr()

◆ parseCondBranch()

◆ STATISTIC() [1/2]

STATISTIC ( NumVRegReloaded ,
"Number of registers within vector register groups reloaded" )

◆ STATISTIC() [2/2]

STATISTIC ( NumVRegSpilled ,
"Number of registers within vector register groups spilled" )

◆ ForceMachineCombinerStrategy

cl::opt< MachineTraceStrategy > ForceMachineCombinerStrategy("riscv-force-machine-combiner-strategy", cl::Hidden, cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation."), cl::init(MachineTraceStrategy::TS_NumStrategies), cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy."))) ( "riscv-force-machine-combiner-strategy" , cl::Hidden , cl::desc("Force machine combiner to use a specific strategy for machine " "trace metrics evaluation.") , cl::init(MachineTraceStrategy::TS_NumStrategies) , cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local", "Local strategy."), clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr", "MinInstrCount strategy.")) ) static

◆ PreferWholeRegisterMove

cl::opt< bool > PreferWholeRegisterMove("riscv-prefer-whole-register-move", cl::init(false), cl::Hidden, cl::desc("Prefer whole register move for vector registers.")) ( "riscv-prefer-whole-register-move" , cl::init(false) , cl::Hidden , cl::desc("Prefer whole register move for vector registers.") ) static