RISCVMCTargetDesc.cpp Source File (original) (raw)

34#include

36#define GET_INSTRINFO_MC_DESC

37#define ENABLE_INSTR_PREDICATE_VERIFIER

38#include "RISCVGenInstrInfo.inc"

40#define GET_REGINFO_MC_DESC

41#include "RISCVGenRegisterInfo.inc"

43#define GET_SUBTARGETINFO_MC_DESC

44#include "RISCVGenSubtargetInfo.inc"

46using namespace llvm;

50 InitRISCVMCInstrInfo(X);

51 return X;

52}

56 InitRISCVMCRegisterInfo(X, RISCV::X1);

57 return X;

58}

65 unsigned SP = MRI.getDwarfRegNum(RISCV::X2, true);

69 return MAI;

70}

74 bool LargeCodeModel = false) {

77 return MOFI;

78}

82 if (CPU.empty() || CPU == "generic")

83 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";

86 createRISCVMCSubtargetInfoImpl(TT, CPU, CPU, FS);

91 if (CPU == "help") {

93 if (TT.isArch64Bit())

94 Features.set(RISCV::Feature64Bit);

95 else

96 Features.set(RISCV::Feature32Bit);

97 X->setFeatureBits(Features);

98 }

100 return X;

101}

102

104 unsigned SyntaxVariant,

109}

110

114 if (TT.isOSBinFormatELF())

116 return nullptr;

117}

118

124

128

129namespace {

130

132 int64_t GPRState[31] = {};

133 std::bitset<31> GPRValidMask;

134

135 static bool isGPR(MCRegister Reg) {

136 return Reg >= RISCV::X0 && Reg <= RISCV::X31;

137 }

138

139 static unsigned getRegIndex(MCRegister Reg) {

140 assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");

141 return Reg - RISCV::X1;

142 }

143

144 void setGPRState(MCRegister Reg, std::optional<int64_t> Value) {

145 if (Reg == RISCV::X0)

146 return;

147

148 auto Index = getRegIndex(Reg);

149

152 GPRValidMask.set(Index);

153 } else {

154 GPRValidMask.reset(Index);

155 }

156 }

157

158 std::optional<int64_t> getGPRState(MCRegister Reg) const {

159 if (Reg == RISCV::X0)

160 return 0;

161

162 auto Index = getRegIndex(Reg);

163

164 if (GPRValidMask.test(Index))

165 return GPRState[Index];

166 return std::nullopt;

167 }

168

169public:

170 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)

171 : MCInstrAnalysis(Info) {}

172

173 void resetState() override { GPRValidMask.reset(); }

174

175 void updateState(const MCInst &Inst, uint64_t Addr) override {

176

177

178

179

180

181 if (isTerminator(Inst) || isCall(Inst)) {

182 resetState();

183 return;

184 }

185

187 default: {

188

189

190 auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();

191 for (unsigned I = 0; I < NumDefs; ++I) {

193 if (isGPR(DefReg))

194 setGPRState(DefReg, std::nullopt);

195 }

196 break;

197 }

198 case RISCV::AUIPC:

201 break;

202 }

203 }

204

205 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,

206 uint64_t &Target) const override {

207 if (isConditionalBranch(Inst)) {

208 int64_t Imm;

209 if (Size == 2)

211 else

214 return true;

215 }

216

218 case RISCV::C_J:

219 case RISCV::C_JAL:

220 case RISCV::QC_E_J:

221 case RISCV::QC_E_JAL:

223 return true;

224 case RISCV::JAL:

226 return true;

227 case RISCV::JALR: {

228 if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {

230 return true;

231 }

232 return false;

233 }

234 }

235

236 return false;

237 }

238

239 bool isTerminator(const MCInst &Inst) const override {

241 return true;

242

244 default:

245 return false;

246 case RISCV::JAL:

247 case RISCV::JALR:

249 }

250 }

251

252 bool isCall(const MCInst &Inst) const override {

254 return true;

255

257 default:

258 return false;

259 case RISCV::JAL:

260 case RISCV::JALR:

262 }

263 }

264

265 bool isReturn(const MCInst &Inst) const override {

267 return true;

268

270 default:

271 return false;

272 case RISCV::JALR:

275 case RISCV::C_JR:

277 }

278 }

279

280 bool isBranch(const MCInst &Inst) const override {

282 return true;

283

284 return isBranchImpl(Inst);

285 }

286

289 return true;

290

291 return isBranchImpl(Inst);

292 }

293

294 bool isIndirectBranch(const MCInst &Inst) const override {

296 return true;

297

299 default:

300 return false;

301 case RISCV::JALR:

304 case RISCV::C_JR:

306 }

307 }

308

309

310 std::vector<std::pair<uint64_t, uint64_t>>

311 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,

312 const MCSubtargetInfo &STI) const override {

313 uint32_t LoadInsnOpCode;

315 LoadInsnOpCode = 0x3003;

316 else if (T.isRISCV32())

317 LoadInsnOpCode = 0x2003;

318 else

319 return {};

320

321 constexpr uint64_t FirstEntryAt = 32, EntrySize = 16;

322 if (PltContents.size() < FirstEntryAt + EntrySize)

323 return {};

324

325 std::vector<std::pair<uint64_t, uint64_t>> Results;

326 for (uint64_t EntryStart = FirstEntryAt,

327 EntryStartEnd = PltContents.size() - EntrySize;

328 EntryStart <= EntryStartEnd; EntryStart += EntrySize) {

329 const uint32_t AuipcInsn =

331 const bool IsAuipc = (AuipcInsn & 0x7F) == 0x17;

332 if (!IsAuipc)

333 continue;

334

335 const uint32_t LoadInsn =

337 const bool IsLoad = (LoadInsn & 0x707F) == LoadInsnOpCode;

338 if (!IsLoad)

339 continue;

340

341 const uint64_t GotPltSlotVA = PltSectionVA + EntryStart +

342 (AuipcInsn & 0xFFFFF000) +

344 Results.emplace_back(PltSectionVA + EntryStart, GotPltSlotVA);

345 }

346

348 }

349

350private:

351 static bool maybeReturnAddress(MCRegister Reg) {

352

353 return Reg == RISCV::X1 || Reg == RISCV::X5;

354 }

355

356 static bool isBranchImpl(const MCInst &Inst) {

358 default:

359 return false;

360 case RISCV::JAL:

362 case RISCV::JALR:

365 case RISCV::C_JR:

367 }

368 }

369};

370

371}

372

374 return new RISCVMCInstrAnalysis(Info);

375}

376

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isUnconditionalBranch(Instruction *Term)

Function Alias Analysis Results

Analysis containing CSE Info

#define LLVM_EXTERNAL_VISIBILITY

PassInstrumentationCallbacks PIC

static bool isBranch(unsigned Opcode)

static MCRegisterInfo * createRISCVMCRegisterInfo(const Triple &TT)

Definition RISCVMCTargetDesc.cpp:54

static MCInstPrinter * createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)

Definition RISCVMCTargetDesc.cpp:103

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC()

Definition RISCVMCTargetDesc.cpp:378

static MCObjectFileInfo * createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, bool LargeCodeModel=false)

Definition RISCVMCTargetDesc.cpp:73

static MCTargetStreamer * createRISCVNullTargetStreamer(MCStreamer &S)

Definition RISCVMCTargetDesc.cpp:125

static MCSubtargetInfo * createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)

Definition RISCVMCTargetDesc.cpp:80

static MCTargetStreamer * createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)

Definition RISCVMCTargetDesc.cpp:112

static MCInstrAnalysis * createRISCVInstrAnalysis(const MCInstrInfo *Info)

Definition RISCVMCTargetDesc.cpp:373

static MCTargetStreamer * createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)

Definition RISCVMCTargetDesc.cpp:120

static MCInstrInfo * createRISCVMCInstrInfo()

Definition RISCVMCTargetDesc.cpp:48

static MCAsmInfo * createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)

Definition RISCVMCTargetDesc.cpp:60

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

size_t size() const

size - Get the array size.

Container class for subtarget features.

This class is intended to be used as a base class for asm properties and features specific to the tar...

void addInitialFrameState(const MCCFIInstruction &Inst)

static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})

.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.

Context object for machine code objects.

This is an instance of a target assembly language printer that converts an MCInst to valid target ass...

unsigned getOpcode() const

const MCOperand & getOperand(unsigned i) const

virtual bool isCall(const MCInst &Inst) const

virtual bool isBranch(const MCInst &Inst) const

virtual bool isUnconditionalBranch(const MCInst &Inst) const

virtual bool isTerminator(const MCInst &Inst) const

virtual bool isReturn(const MCInst &Inst) const

virtual bool isIndirectBranch(const MCInst &Inst) const

Interface to description of machine instruction set.

void initMCObjectFileInfo(MCContext &MCCtx, bool PIC, bool LargeCodeModel=false)

MCRegister getReg() const

Returns the register number.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Streaming machine code generation interface.

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

Target specific streamer interface.

StringRef - Represent a constant reference to a string, i.e.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

bool isRISCV64() const

Tests whether the target is 64-bit RISC-V.

formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...

uint32_t read32le(const void *P)

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

Target & getTheRISCV32Target()

Target & getTheRISCV64beTarget()

MCStreamer * createRISCVELFStreamer(const Triple &, MCContext &C, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)

MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Target & getTheRISCV64Target()

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.

Target & getTheRISCV32beTarget()

static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)

RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.

static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)

RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.

static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)

RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.

static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)

RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.

static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)

RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.

static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)

static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)

RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.

static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)

static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)

static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)

RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.

static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)

RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.

static void RegisterMCObjectFileInfo(Target &T, Target::MCObjectFileInfoCtorFnTy Fn)

static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)