RISCVRedundantCopyElimination.cpp Source File (original) (raw)

33using namespace llvm;

35#define DEBUG_TYPE "riscv-copyelim"

37 STATISTIC(NumCopiesRemoved, "Number of copies removed.");

39namespace {

45public:

46 static char ID;

49 bool runOnMachineFunction(MachineFunction &MF) override;

50 MachineFunctionProperties getRequiredProperties() const override {

51 return MachineFunctionProperties().setNoVRegs();

52 }

54 StringRef getPassName() const override {

55 return "RISC-V Redundant Copy Elimination";

56 }

58private:

60};

62}

64char RISCVRedundantCopyElimination::ID = 0;

67 "RISC-V Redundant Copy Elimination", false, false)

69static bool

73 assert(Cond.size() == 3 && "Unexpected number of operands");

74 assert(TBB != nullptr && "Expected branch target basic block");

78 return true;

81 return true;

82 return false;

83}

88 return false;

94 return false;

96 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;

100 return false;

101

102

103 if (!guaranteesZeroRegInBlock(MBB, Cond, TBB))

104 return false;

105

107 if (!TargetReg)

108 return false;

109

112

114 MachineInstr *MI = &*I;

115 ++I;

116 if (MI->isCopy() && MI->getOperand(0).isReg() &&

117 MI->getOperand(1).isReg()) {

118 Register DefReg = MI->getOperand(0).getReg();

119 Register SrcReg = MI->getOperand(1).getReg();

120

121 if (SrcReg == RISCV::X0 && MRI ->isReserved(DefReg) &&

122 TargetReg == DefReg) {

125

126 MI->eraseFromParent();

128 LastChange = I;

129 ++NumCopiesRemoved;

130 continue;

131 }

132 }

133

134 if (MI->modifiesRegister(TargetReg, TRI))

135 break;

136 }

137

139 return false;

140

142 assert((CondBr->getOpcode() == RISCV::BEQ ||

143 CondBr->getOpcode() == RISCV::BNE) &&

144 "Unexpected opcode");

145 assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register");

146

147

148

149 CondBr->clearRegisterKills(TargetReg, TRI);

150

151

154

155

157 MMI.clearRegisterKills(TargetReg, TRI);

158

159 return true;

160}

161

162bool RISCVRedundantCopyElimination::runOnMachineFunction(MachineFunction &MF) {

164 return false;

165

169

171 for (MachineBasicBlock &MBB : MF)

173

175}

176

178 return new RISCVRedundantCopyElimination();

179}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

Promote Memory to Register

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

static bool isReg(const MCInst &MI, unsigned OpNo)

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

Definition RISCVRedundantCopyElimination.cpp:72

const SmallVectorImpl< MachineOperand > & Cond

Definition RISCVRedundantCopyElimination.cpp:71

assert(TBB !=nullptr &&"Expected branch target basic block")

auto Opc

Definition RISCVRedundantCopyElimination.cpp:75

static bool optimizeBlock(BasicBlock &BB, bool &ModifiedDT, const TargetTransformInfo &TTI, const DataLayout &DL, bool HasBranchDivergence, DomTreeUpdater *DTU)

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

FunctionPass class - This class is used to implement most global optimizations.

unsigned pred_size() const

LLVM_ABI iterator getFirstTerminator()

Returns an iterator to the first terminator instruction of this basic block.

unsigned succ_size() const

pred_iterator pred_begin()

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

MachineInstrBundleIterator< MachineInstr > iterator

LLVM_ABI bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const

Return true if the specified register is in the live in set.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

virtual void print(raw_ostream &OS, const Module *M) const

print - Print out the internal state of the pass.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

TargetInstrInfo - Interface to description of machine instruction set.

virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

FunctionPass * createRISCVRedundantCopyEliminationPass()

Definition RISCVRedundantCopyElimination.cpp:177

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...