RISCVRegisterInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H

14#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H

19#define GET_REGINFO_HEADER

20#include "RISCVGenRegisterInfo.inc"

22namespace llvm {

38};

41enum {

45};

62}

75 return 5;

76 }

98 unsigned FIOperandNum,

100

102

104

106 int64_t Offset) const override;

107

109 int64_t Offset) const override;

110

112 int64_t Offset) const override;

113

115 int Idx) const override;

116

118 bool IsSpill) const;

119

121

123

127

131

134 return &RISCV::GPRRegClass;

135 }

136

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163

167

171};

172}

173

174#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

uint64_t IntrinsicInst * II

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Wrapper class representing physical registers. Should be passed by value.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StackOffset holds a fixed and a scalable offset in bytes.

StringRef - Represent a constant reference to a string, i.e.

const uint8_t TSFlags

Configurable target specific flags.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Definition RISCVRegisterInfo.h:24

@ RegPairOdd

Definition RISCVRegisterInfo.h:43

@ RegPairEven

Definition RISCVRegisterInfo.h:44

static unsigned getNF(uint8_t TSFlags)

Definition RISCVRegisterInfo.h:59

@ IsVRegClassShiftMask

Definition RISCVRegisterInfo.h:28

@ NFShiftMask

Definition RISCVRegisterInfo.h:37

@ NFShift

Definition RISCVRegisterInfo.h:36

@ VLMulShiftMask

Definition RISCVRegisterInfo.h:32

@ VLMulShift

Definition RISCVRegisterInfo.h:31

@ IsVRegClassShift

Definition RISCVRegisterInfo.h:27

static bool isVRegClass(uint8_t TSFlags)

Definition RISCVRegisterInfo.h:48

static RISCVVType::VLMUL getLMul(uint8_t TSFlags)

Definition RISCVRegisterInfo.h:53

This is an optimization pass for GlobalISel generic memory operations.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.

bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override

bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override

bool requiresRegisterScavenging(const MachineFunction &MF) const override

Definition RISCVRegisterInfo.h:124

const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override

const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override

BitVector getReservedRegs(const MachineFunction &MF) const override

unsigned getCSRFirstUseCost() const override

Definition RISCVRegisterInfo.h:71

const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override

static bool isVRNRegClass(const TargetRegisterClass *RC)

Definition RISCVRegisterInfo.h:164

bool requiresFrameIndexScavenging(const MachineFunction &MF) const override

Definition RISCVRegisterInfo.h:128

RISCVRegisterInfo(unsigned HwMode)

void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override

bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override

static bool isRVVRegClass(const TargetRegisterClass *RC)

Definition RISCVRegisterInfo.h:168

const MCPhysReg * getIPRACSRegs(const MachineFunction *MF) const override

void lowerSegmentSpillReload(MachineBasicBlock::iterator II, bool IsSpill) const

const TargetRegisterClass * getPointerRegClass(unsigned Kind=0) const override

Definition RISCVRegisterInfo.h:133

void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const

void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const override

bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override

const uint32_t * getNoPreservedMask() const override

float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override

static bool isVRRegClass(const TargetRegisterClass *RC)

Definition RISCVRegisterInfo.h:159

void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override

bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override

int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override

unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override

StringRef getRegAsmName(MCRegister Reg) const override

bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override