RISCVTargetMachine.cpp Source File (original) (raw)

42#include

43using namespace llvm;

46 "riscv-enable-copyelim",

47 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),

53 cl::desc("Enable the global merge pass"));

57 cl::desc("Enable the machine combiner pass"),

61 "riscv-v-vector-bits-max",

62 cl::desc("Assume V extension vector registers are at most this big, "

63 "with zero meaning no maximum size is assumed."),

67 "riscv-v-vector-bits-min",

68 cl::desc("Assume V extension vector registers are at least this big, "

69 "with zero meaning no minimum size is assumed. A value of -1 "

70 "means use Zvl*b extension. This is primarily used to enable "

71 "autovectorization with fixed width vectors."),

75 "riscv-enable-copy-propagation",

76 cl::desc("Enable the copy propagation with RISC-V copy instr"),

81 cl::desc("Enable the pass that removes dead"

82 " definitions and replaces stores to"

83 " them with stores to x0"),

88 cl::desc("Enable sinking and folding of instruction copies"),

93 cl::desc("Enable the loop data prefetch pass"),

97 "riscv-disable-vector-mask-mutation",

98 cl::desc("Disable the vector mask scheduling mutation"), cl::init(false),

100

103 cl::desc("Enable Machine Pipeliner for RISC-V"),

105

107 "riscv-enable-cfi-instr-inserter",

108 cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false),

110

150

154

158 std::optionalReloc::Model RM,

159 std::optionalCodeModel::Model CM,

162 T, TT.computeDataLayout(Options.MCOptions.getABIName()), TT, CPU, FS,

167

168

171

172

174

175 if (TT.isOSFuchsia() && !TT.isArch64Bit())

177

179}

180

183 Attribute CPUAttr = F.getFnAttribute("target-cpu");

184 Attribute TuneAttr = F.getFnAttribute("tune-cpu");

185 Attribute FSAttr = F.getFnAttribute("target-features");

186

187 std::string CPU =

189 std::string TuneCPU =

191 std::string FS =

193

196

197 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);

198 if (VScaleRangeAttr.isValid()) {

201 std::optional VScaleMax = VScaleRangeAttr.getVScaleRangeMax();

204 }

205

206 if (RVVBitsMin != -1U) {

207

208 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&

210 "V or Zve* extension requires vector length to be in the range of "

211 "64 to 65536 and a power 2!");

212 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&

213 "Minimum V extension vector length should not be larger than its "

214 "maximum!");

215 }

216 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&

218 "V or Zve* extension requires vector length to be in the range of "

219 "64 to 65536 and a power 2!");

220

221 if (RVVBitsMin != -1U) {

222 if (RVVBitsMax != 0) {

223 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);

224 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);

225 }

226

228 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);

229 }

230 RVVBitsMax =

231 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);

232

235 << CPU << TuneCPU << FS;

236 auto &I = SubtargetMap[Key];

237 if () {

238

239

240

242 auto ABIName = Options.MCOptions.getABIName();

244 F.getParent()->getModuleFlag("target-abi"))) {

247 ModuleTargetABI->getString() != ABIName) {

249 }

250 ABIName = ModuleTargetABI->getString();

251 }

252 I = std::make_unique(

253 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);

254 }

255 return I.get();

256}

257

264

269

270

271

272

273

275 unsigned DstAS) const {

276 return true;

277}

278

283

284 if (ST.enableMISchedLoadClustering())

286 DAG->TII, DAG->TRI, true));

287

288 if (ST.enableMISchedStoreClustering())

290 DAG->TII, DAG->TRI, true));

291

294

295 return DAG;

296}

297

302

303 if (ST.enablePostMISchedLoadClustering())

305 DAG->TII, DAG->TRI, true));

306

307 if (ST.enablePostMISchedStoreClustering())

309 DAG->TII, DAG->TRI, true));

310

311 return DAG;

312}

313

314namespace {

315

316class RVVRegisterRegAlloc : public RegisterRegAllocBase {

317public:

320};

321

327}

328

330

331static llvm::once_flag InitializeDefaultRVVRegisterAllocatorFlag;

332

333

334

335

336static cl::opt<RVVRegisterRegAlloc::FunctionPassCtor, false,

338 RVVRegAlloc("riscv-rvv-regalloc", cl::Hidden,

340 cl::desc("Register allocator to use for RVV register."));

341

342static void initializeDefaultRVVRegisterAllocatorOnce() {

344

345 if (!Ctor) {

346 Ctor = RVVRegAlloc;

347 RVVRegisterRegAlloc::setDefault(RVVRegAlloc);

348 }

349}

350

351static FunctionPass *createBasicRVVRegisterAllocator() {

353}

354

355static FunctionPass *createGreedyRVVRegisterAllocator() {

357}

358

359static FunctionPass *createFastRVVRegisterAllocator() {

361}

362

363static RVVRegisterRegAlloc basicRegAllocRVVReg("basic",

364 "basic register allocator",

365 createBasicRVVRegisterAllocator);

366static RVVRegisterRegAlloc

367 greedyRegAllocRVVReg("greedy", "greedy register allocator",

368 createGreedyRVVRegisterAllocator);

369

370static RVVRegisterRegAlloc fastRegAllocRVVReg("fast", "fast register allocator",

371 createFastRVVRegisterAllocator);

372

374public:

375 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)

376 : TargetPassConfig(TM, PM) {

377 if (TM.getOptLevel() != CodeGenOptLevel::None)

380 EnableLoopTermFold = true;

381 }

382

383 RISCVTargetMachine &getRISCVTargetMachine() const {

385 }

386

387 void addIRPasses() override;

388 bool addPreISel() override;

389 void addCodeGenPrepare() override;

390 bool addInstSelector() override;

391 bool addIRTranslator() override;

392 void addPreLegalizeMachineIR() override;

393 bool addLegalizeMachineIR() override;

394 void addPreRegBankSelect() override;

395 bool addRegBankSelect() override;

396 bool addGlobalInstructionSelect() override;

397 void addPreEmitPass() override;

398 void addPreEmitPass2() override;

399 void addPreSched2() override;

400 void addMachineSSAOptimization() override;

401 FunctionPass *createRVVRegAllocPass(bool Optimized);

402 bool addRegAssignAndRewriteFast() override;

403 bool addRegAssignAndRewriteOptimized() override;

404 void addPreRegAlloc() override;

405 void addPostRegAlloc() override;

406 void addFastRegAlloc() override;

407 bool addILPOpts() override;

408

409 std::unique_ptr getCSEConfig() const override;

410};

411}

412

414 return new RISCVPassConfig(*this, PM);

415}

416

417std::unique_ptr RISCVPassConfig::getCSEConfig() const {

419}

420

421FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {

422

423 llvm::call_once(InitializeDefaultRVVRegisterAllocatorFlag,

424 initializeDefaultRVVRegisterAllocatorOnce);

425

428 return Ctor();

429

430 if (Optimized)

431 return createGreedyRVVRegisterAllocator();

432

433 return createFastRVVRegisterAllocator();

434}

435

436bool RISCVPassConfig::addRegAssignAndRewriteFast() {

437 addPass(createRVVRegAllocPass(false));

443}

444

445bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {

446 addPass(createRVVRegAllocPass(true));

453}

454

455void RISCVPassConfig::addIRPasses() {

458

462

466 }

467

469}

470

471bool RISCVPassConfig::addPreISel() {

475

476

477

479 }

480

484

485

486

487

489 false,

490 true));

491 }

492

493 return false;

494}

495

496void RISCVPassConfig::addCodeGenPrepare() {

500}

501

502bool RISCVPassConfig::addInstSelector() {

504

505 return false;

506}

507

508bool RISCVPassConfig::addIRTranslator() {

510 return false;

511}

512

513void RISCVPassConfig::addPreLegalizeMachineIR() {

516 } else {

518 }

519}

520

521bool RISCVPassConfig::addLegalizeMachineIR() {

523 return false;

524}

525

526void RISCVPassConfig::addPreRegBankSelect() {

529}

530

531bool RISCVPassConfig::addRegBankSelect() {

533 return false;

534}

535

536bool RISCVPassConfig::addGlobalInstructionSelect() {

538 return false;

539}

540

541void RISCVPassConfig::addPreSched2() {

543

544

548}

549

550void RISCVPassConfig::addPreEmitPass() {

551

552

553

554

555

561

562

563

567}

568

569void RISCVPassConfig::addPreEmitPass2() {

572

573

575 }

577

578

579

580

582

583

586 }));

587

590}

591

592void RISCVPassConfig::addMachineSSAOptimization() {

595

597

598 if (TM->getTargetTriple().isRISCV64()) {

600 }

601}

602

603void RISCVPassConfig::addPreRegAlloc() {

608

610 }

611

615

618

620}

621

622void RISCVPassConfig::addFastRegAlloc() {

625}

626

627

628void RISCVPassConfig::addPostRegAlloc() {

632}

633

634bool RISCVPassConfig::addILPOpts() {

637

638 return true;

639}

640

642#define GET_PASS_REGISTRY "RISCVPassRegistry.def"

644

645 PB.registerLateLoopOptimizationsEPCallback([=](LoopPassManager &LPM,

649 });

650}

651

656

662

666 const auto &YamlMFI =

669 return false;

670}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))

static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)

static Reloc::Model getEffectiveRelocModel()

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Provides analysis for continuously CSEing during GISel passes.

#define LLVM_EXTERNAL_VISIBILITY

static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))

This file declares the IRTranslator pass.

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableMachinePipeliner("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden)

static cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))

static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)

static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))

static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)

static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)

static cl::opt< bool > DisableVectorMaskMutation("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden)

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()

Definition RISCVTargetMachine.cpp:111

static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0"), cl::init(true))

static cl::opt< bool > EnableCFIInstrInserter("riscv-enable-cfi-instr-inserter", cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false), cl::Hidden)

static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

This file defines a TargetTransformInfoImplBase conforming object specific to the RISC-V target machi...

This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...

const GCNTargetMachine & getTM(const GCNSubtarget *STI)

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

static FunctionPass * useDefaultRegisterAllocator()

-regalloc=... command line option.

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

Functions, function parameters, and return types can have attributes to indicate how they should be t...

LLVM_ABI std::optional< unsigned > getVScaleRangeMax() const

Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.

LLVM_ABI unsigned getVScaleRangeMin() const

Returns the minimum value for the vscale_range attribute.

LLVM_ABI StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)

Lightweight error class with error context and mandatory checking.

FunctionPass class - This class is used to implement most global optimizations.

Module * getParent()

Get the module that this global value is contained inside of...

This pass is responsible for selecting generic machine instructions to target-specific instructions.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Metadata * getModuleFlag(StringRef Key) const

Return the corresponding value if Key appears in module flags, otherwise return null.

static LLVM_ABI const OptimizationLevel O0

Disable as many optimizations as possible.

This class provides access to building LLVM's passes.

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

This implementation is used for RISC-V ELF targets.

RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...

yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override

Allocate and return a default initialized instance of the YAML representation for the MachineFunction...

Definition RISCVTargetMachine.cpp:653

RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Definition RISCVTargetMachine.cpp:155

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

Definition RISCVTargetMachine.cpp:413

void registerPassBuilderCallbacks(PassBuilder &PB) override

Allow the target to modify the pass pipeline.

Definition RISCVTargetMachine.cpp:641

bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override

Returns true if a cast between SrcAS and DestAS is a noop.

Definition RISCVTargetMachine.cpp:274

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

Definition RISCVTargetMachine.cpp:266

ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...

Definition RISCVTargetMachine.cpp:280

ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Definition RISCVTargetMachine.cpp:299

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

Definition RISCVTargetMachine.cpp:258

yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.

Definition RISCVTargetMachine.cpp:658

bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override

Parse out the target's MachineFunctionInfo from the YAML reprsentation.

Definition RISCVTargetMachine.cpp:663

const RISCVSubtarget * getSubtargetImpl() const =delete

This pass implements the reg bank selector pass used in the GlobalISel pipeline.

RegisterPassParser class - Handle the addition of new machine passes.

RegisterRegAllocBase class - Track the registration of register allocators.

FunctionPass *(*)() FunctionPassCtor

Wrapper class representing virtual and physical registers.

Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...

Represents a range in source code.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

void setSupportsDebugEntryValues(bool Enable)

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

void setMachineOutliner(bool Enable)

void setCFIFixup(bool Enable)

void setSupportsDefaultOutlining(bool Enable)

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

Target-Independent Code Generator Pass Configuration Options.

virtual void addCodeGenPrepare()

Add pass to prepare the LLVM IR for code generation.

virtual bool addRegAssignAndRewriteFast()

Add core register allocator passes which do the actual register assignment and rewriting.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

virtual void addFastRegAlloc()

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...

virtual void addMachineSSAOptimization()

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

virtual bool addRegAssignAndRewriteOptimized()

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

A raw_ostream that writes to an SmallVector or SmallString.

Interfaces for registering analysis passes, producing common pass manager configurations,...

@ C

The default llvm calling convention, compatible with C.

ABI getTargetABI(StringRef ABIName)

static constexpr unsigned RVVBitsPerBlock

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

ScheduleDAGMILive * createSchedLive(MachineSchedContext *C)

Create the standard converging machine scheduler.

FunctionPass * createRISCVLandingPadSetupPass()

FunctionPass * createRISCVLoadStoreOptPass()

LLVM_ABI FunctionPass * createFastRegisterAllocator()

FastRegisterAllocation Pass - This pass register allocates as fast as possible.

void initializeRISCVPushPopOptPass(PassRegistry &)

void initializeRISCVExpandPseudoPass(PassRegistry &)

FunctionPass * createRISCVFoldMemOffsetPass()

FunctionPass * createRISCVMoveMergePass()

createRISCVMoveMergePass - returns an instance of the move merge pass.

LLVM_ABI char & InitUndefID

LLVM_ABI FunctionPass * createTypePromotionLegacyPass()

Create IR Type Promotion pass.

void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)

LLVM_ABI FunctionPass * createGreedyRegisterAllocator()

Greedy register allocation pass - This pass implements a global register allocator for optimized buil...

void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)

FunctionPass * createRISCVCodeGenPrepareLegacyPass()

FunctionPass * createRISCVExpandAtomicPseudoPass()

FunctionPass * createRISCVPostRAExpandPseudoPass()

LLVM_ABI Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false, bool MergeConstantByDefault=false, bool MergeConstAggressiveByDefault=false)

GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...

FunctionPass * createRISCVInsertReadWriteCSRPass()

Target & getTheRISCV32Target()

void initializeRISCVFoldMemOffsetPass(PassRegistry &)

void initializeRISCVInsertVSETVLIPass(PassRegistry &)

FunctionPass * createRISCVVLOptimizerPass()

LLVM_ABI char & PostRASchedulerID

PostRAScheduler - This pass performs post register allocation scheduling.

void initializeRISCVLateBranchOptPass(PassRegistry &)

void initializeRISCVRedundantCopyEliminationPass(PassRegistry &)

Target & getTheRISCV64beTarget()

LLVM_ABI std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)

FunctionPass * createRISCVDeadRegisterDefinitionsPass()

LLVM_ABI char & PostMachineSchedulerID

PostMachineScheduler - This pass schedules machine instructions postRA.

FunctionPass * createRISCVGatherScatterLoweringPass()

FunctionPass * createRISCVMergeBaseOffsetOptPass()

Returns an instance of the Merge Base Offset Optimization pass.

auto dyn_cast_or_null(const Y &Val)

FunctionPass * createRISCVPostLegalizerCombiner()

PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & > LoopPassManager

The Loop pass manager.

LLVM_ABI char & MachineCombinerID

This pass performs instruction combining using trace metrics to estimate critical-path and resource d...

static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)

void initializeRISCVPostRAExpandPseudoPass(PassRegistry &)

CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)

Helper method for getting the code model, returning Default if CM does not have a value.

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

ScheduleDAGMI * createSchedPostRA(MachineSchedContext *C)

Create a generic scheduler with no vreg liveness or DAG mutation passes.

LLVM_ABI char & BranchRelaxationPassID

BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...

void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &)

FunctionPass * createRISCVPreAllocZilsdOptPass()

FunctionPass * createRISCVPushPopOptimizationPass()

createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.

FunctionPass * createRISCVMakeCompressibleOptPass()

Returns an instance of the Make Compressible Optimization pass.

FunctionPass * createRISCVRedundantCopyEliminationPass()

LLVM_ABI FunctionPass * createKCFIPass()

Lowers KCFI operand bundles for indirect calls.

void initializeRISCVVMV0EliminationPass(PassRegistry &)

void initializeRISCVInsertWriteVXRMPass(PassRegistry &)

void initializeRISCVLoadStoreOptPass(PassRegistry &)

LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)

If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...

LLVM_ABI FunctionPass * createLoopDataPrefetchPass()

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)

void initializeRISCVExpandAtomicPseudoPass(PassRegistry &)

FunctionPass * createRISCVPreLegalizerCombiner()

void initializeRISCVCodeGenPrepareLegacyPassPass(PassRegistry &)

FunctionPass * createRISCVVMV0EliminationPass()

FunctionPass * createRISCVInsertVSETVLIPass()

Returns an instance of the Insert VSETVLI pass.

FunctionPass * createRISCVO0PreLegalizerCombiner()

CodeGenOptLevel

Code generation optimization level.

LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key

FunctionPass * createRISCVIndirectBranchTrackingPass()

FunctionPass * createRISCVOptWInstrsPass()

LLVM_ABI FunctionPass * createInterleavedAccessPass()

InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...

std::unique_ptr< ScheduleDAGMutation > createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI)

LLVM_ABI FunctionPass * createBasicRegisterAllocator()

BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...

LLVM_ABI void initializeGlobalISel(PassRegistry &)

Initialize all passes linked into the GlobalISel library.

LLVM_ABI void initializeKCFIPass(PassRegistry &)

void initializeRISCVMakeCompressibleOptPass(PassRegistry &)

LLVM_ABI char & MachinePipelinerID

This pass performs software pipelining on machine instructions.

LLVM_ABI ModulePass * createBarrierNoopPass()

createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.

void initializeRISCVVLOptimizerPass(PassRegistry &)

LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)

If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...

void initializeRISCVOptWInstrsPass(PassRegistry &)

LLVM_ABI FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)

FunctionPass * createRISCVLateBranchOptPass()

Target & getTheRISCV64Target()

ModulePass * createRISCVPromoteConstantPass()

FunctionPass * createRISCVVectorPeepholePass()

void call_once(once_flag &flag, Function &&F, Args &&... ArgList)

Execute the function specified as a parameter once.

void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)

void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)

void initializeRISCVIndirectBranchTrackingPass(PassRegistry &)

void initializeRISCVPromoteConstantPass(PassRegistry &)

void initializeRISCVAsmPrinterPass(PassRegistry &)

FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)

LLVM_ABI FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)

void initializeRISCVGatherScatterLoweringPass(PassRegistry &)

FunctionPass * createRISCVExpandPseudoPass()

FunctionPass * createRISCVPreRAExpandPseudoPass()

LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

T bit_floor(T Value)

Returns the largest integral power of two no greater than Value if Value is nonzero.

FunctionPass * createRISCVInsertWriteVXRMPass()

LLVM_ABI MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)

void initializeRISCVVectorPeepholePass(PassRegistry &)

FunctionPass * createRISCVZacasABIFixPass()

LLVM_ABI FunctionPass * createCFIInstrInserter()

Creates CFI Instruction Inserter pass.

void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)

void initializeRISCVPreAllocZilsdOptPass(PassRegistry &)

Target & getTheRISCV32beTarget()

void initializeRISCVPostLegalizerCombinerPass(PassRegistry &)

void initializeRISCVMoveMergePass(PassRegistry &)

Implement std::hash so that hash_code can be used in STL containers.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)

Factory function: default behavior is to call new using the supplied allocator.

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

static bool isRVVRegClass(const TargetRegisterClass *RC)

RegisterTargetMachine - Helper template for registering a target machine implementation,...

The llvm::once_flag structure.

Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.