RISCVTargetMachine.cpp Source File (original) (raw)

41#include

42using namespace llvm;

45 "riscv-enable-copyelim",

46 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),

52 cl::desc("Enable the global merge pass"));

56 cl::desc("Enable the machine combiner pass"),

60 "riscv-v-vector-bits-max",

61 cl::desc("Assume V extension vector registers are at most this big, "

62 "with zero meaning no maximum size is assumed."),

66 "riscv-v-vector-bits-min",

67 cl::desc("Assume V extension vector registers are at least this big, "

68 "with zero meaning no minimum size is assumed. A value of -1 "

69 "means use Zvl*b extension. This is primarily used to enable "

70 "autovectorization with fixed width vectors."),

74 "riscv-enable-copy-propagation",

75 cl::desc("Enable the copy propagation with RISC-V copy instr"),

80 cl::desc("Enable the pass that removes dead"

81 " definitons and replaces stores to"

82 " them with stores to x0"),

87 cl::desc("Enable sinking and folding of instruction copies"),

92 cl::desc("Enable the loop data prefetch pass"),

96 "riscv-misched-load-store-clustering", cl::Hidden,

97 cl::desc("Enable load and store clustering in the machine scheduler"),

101 "riscv-postmisched-load-store-clustering", cl::Hidden,

102 cl::desc("Enable PostRA load and store clustering in the machine scheduler"),

104

107 cl::desc("Enable the RISC-V VL Optimizer pass"),

109

111 "riscv-disable-vector-mask-mutation",

112 cl::desc("Disable the vector mask scheduling mutation"), cl::init(false),

114

117 cl::desc("Enable Machine Pipeliner for RISC-V"),

119

146}

147

151 if (TT.isArch64Bit()) {

152 if (ABIName == "lp64e")

153 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S64";

154

155 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";

156 }

157 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");

158

159 if (ABIName == "ilp32e")

160 return "e-m:e-p:32:32-i64:64-n32-S32";

161

162 return "e-m:e-p:32:32-i64:64-n32-S128";

163}

164

166 std::optionalReloc::Model RM) {

168}

169

173 std::optionalReloc::Model RM,

174 std::optionalCodeModel::Model CM,

181

182

185

186 if (TT.isOSFuchsia() && !TT.isArch64Bit())

188

190}

191

194 Attribute CPUAttr = F.getFnAttribute("target-cpu");

195 Attribute TuneAttr = F.getFnAttribute("tune-cpu");

196 Attribute FSAttr = F.getFnAttribute("target-features");

197

198 std::string CPU =

200 std::string TuneCPU =

202 std::string FS =

204

207

208 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);

209 if (VScaleRangeAttr.isValid()) {

212 std::optional VScaleMax = VScaleRangeAttr.getVScaleRangeMax();

215 }

216

217 if (RVVBitsMin != -1U) {

218

219 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&

221 "V or Zve* extension requires vector length to be in the range of "

222 "64 to 65536 and a power 2!");

223 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&

224 "Minimum V extension vector length should not be larger than its "

225 "maximum!");

226 }

227 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&

229 "V or Zve* extension requires vector length to be in the range of "

230 "64 to 65536 and a power 2!");

231

232 if (RVVBitsMin != -1U) {

233 if (RVVBitsMax != 0) {

234 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);

235 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);

236 }

237

239 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);

240 }

241 RVVBitsMax =

242 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);

243

245 raw_svector_ostream(Key) << "RVVMin" << RVVBitsMin << "RVVMax" << RVVBitsMax

246 << CPU << TuneCPU << FS;

247 auto &I = SubtargetMap[Key];

248 if () {

249

250

251

254 if (const MDString *ModuleTargetABI = dyn_cast_or_null(

255 F.getParent()->getModuleFlag("target-abi"))) {

258 ModuleTargetABI->getString() != ABIName) {

260 }

261 ABIName = ModuleTargetABI->getString();

262 }

263 I = std::make_unique(

264 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);

265 }

266 return I.get();

267}

268

272 return RISCVMachineFunctionInfo::create(

274}

275

279}

280

281

282

283

284

286 unsigned DstAS) const {

287 return true;

288}

289

290namespace {

291

292class RVVRegisterRegAlloc : public RegisterRegAllocBase {

293public:

296};

297

303}

304

306

307static llvm::once_flag InitializeDefaultRVVRegisterAllocatorFlag;

308

309

310

311

312static cl::opt<RVVRegisterRegAlloc::FunctionPassCtor, false,

314 RVVRegAlloc("riscv-rvv-regalloc", cl::Hidden,

316 cl::desc("Register allocator to use for RVV register."));

317

318static void initializeDefaultRVVRegisterAllocatorOnce() {

320

321 if (!Ctor) {

322 Ctor = RVVRegAlloc;

323 RVVRegisterRegAlloc::setDefault(RVVRegAlloc);

324 }

325}

326

327static FunctionPass *createBasicRVVRegisterAllocator() {

329}

330

331static FunctionPass *createGreedyRVVRegisterAllocator() {

333}

334

335static FunctionPass *createFastRVVRegisterAllocator() {

337}

338

339static RVVRegisterRegAlloc basicRegAllocRVVReg("basic",

340 "basic register allocator",

341 createBasicRVVRegisterAllocator);

342static RVVRegisterRegAlloc

343 greedyRegAllocRVVReg("greedy", "greedy register allocator",

344 createGreedyRVVRegisterAllocator);

345

346static RVVRegisterRegAlloc fastRegAllocRVVReg("fast", "fast register allocator",

347 createFastRVVRegisterAllocator);

348

350public:

353 if (TM.getOptLevel() != CodeGenOptLevel::None)

356 EnableLoopTermFold = true;

357 }

358

360 return getTM();

361 }

362

369 DAG->TII, DAG->TRI, true));

371 DAG->TII, DAG->TRI, true));

372 }

373

378 }

379 return DAG;

380 }

381

388 DAG->TII, DAG->TRI, true));

390 DAG->TII, DAG->TRI, true));

391 }

392 return DAG;

393 }

394

395 void addIRPasses() override;

396 bool addPreISel() override;

397 void addCodeGenPrepare() override;

398 bool addInstSelector() override;

399 bool addIRTranslator() override;

400 void addPreLegalizeMachineIR() override;

401 bool addLegalizeMachineIR() override;

402 void addPreRegBankSelect() override;

403 bool addRegBankSelect() override;

404 bool addGlobalInstructionSelect() override;

405 void addPreEmitPass() override;

406 void addPreEmitPass2() override;

407 void addPreSched2() override;

408 void addMachineSSAOptimization() override;

409 FunctionPass *createRVVRegAllocPass(bool Optimized);

410 bool addRegAssignAndRewriteFast() override;

411 bool addRegAssignAndRewriteOptimized() override;

412 void addPreRegAlloc() override;

413 void addPostRegAlloc() override;

414 void addFastRegAlloc() override;

415

416 std::unique_ptr getCSEConfig() const override;

417};

418}

419

421 return new RISCVPassConfig(*this, PM);

422}

423

424std::unique_ptr RISCVPassConfig::getCSEConfig() const {

426}

427

428FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {

429

430 llvm::call_once(InitializeDefaultRVVRegisterAllocatorFlag,

431 initializeDefaultRVVRegisterAllocatorOnce);

432

435 return Ctor();

436

437 if (Optimized)

438 return createGreedyRVVRegisterAllocator();

439

440 return createFastRVVRegisterAllocator();

441}

442

443bool RISCVPassConfig::addRegAssignAndRewriteFast() {

444 addPass(createRVVRegAllocPass(false));

450}

451

452bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {

453 addPass(createRVVRegAllocPass(true));

460}

461

462void RISCVPassConfig::addIRPasses() {

465

469

473 }

474

476}

477

478bool RISCVPassConfig::addPreISel() {

480

481

482

484 }

485

489

490

491

492

494 false,

495 true));

496 }

497

498 return false;

499}

500

501void RISCVPassConfig::addCodeGenPrepare() {

505}

506

507bool RISCVPassConfig::addInstSelector() {

509

510 return false;

511}

512

513bool RISCVPassConfig::addIRTranslator() {

515 return false;

516}

517

518void RISCVPassConfig::addPreLegalizeMachineIR() {

521 } else {

523 }

524}

525

526bool RISCVPassConfig::addLegalizeMachineIR() {

528 return false;

529}

530

531void RISCVPassConfig::addPreRegBankSelect() {

534}

535

536bool RISCVPassConfig::addRegBankSelect() {

538 return false;

539}

540

541bool RISCVPassConfig::addGlobalInstructionSelect() {

543 return false;

544}

545

546void RISCVPassConfig::addPreSched2() {

548

549

551}

552

553void RISCVPassConfig::addPreEmitPass() {

554

555

556

557

558

564}

565

566void RISCVPassConfig::addPreEmitPass2() {

569

570

572 }

575

576

577

578

580

581

584 }));

585}

586

587void RISCVPassConfig::addMachineSSAOptimization() {

589

591

594

595 if (TM->getTargetTriple().isRISCV64()) {

597 }

598}

599

600void RISCVPassConfig::addPreRegAlloc() {

606 }

607

611

614}

615

616void RISCVPassConfig::addFastRegAlloc() {

619}

620

621

622void RISCVPassConfig::addPostRegAlloc() {

626}

627

632 });

633}

634

638}

639

644}

645

649 const auto &YamlMFI =

652 return false;

653}

unsigned const MachineRegisterInfo * MRI

static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))

static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)

static const Function * getParent(const Value *V)

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

Provides analysis for continuously CSEing during GISel passes.

#define LLVM_EXTERNAL_VISIBILITY

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))

This file declares the IRTranslator pass.

static std::string computeDataLayout()

unsigned const TargetRegisterInfo * TRI

static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableMachinePipeliner("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden)

static cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnablePostMISchedLoadStoreClustering("riscv-postmisched-load-store-clustering", cl::Hidden, cl::desc("Enable PostRA load and store clustering in the machine scheduler"), cl::init(true))

static cl::opt< bool > EnableVLOptimizer("riscv-enable-vl-optimizer", cl::desc("Enable the RISC-V VL Optimizer pass"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))

static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)

static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()

static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)

static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)

static cl::opt< bool > DisableVectorMaskMutation("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden)

static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)

static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))

static cl::opt< bool > EnableMISchedLoadStoreClustering("riscv-misched-load-store-clustering", cl::Hidden, cl::desc("Enable load and store clustering in the machine scheduler"), cl::init(true))

static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...

This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static FunctionPass * useDefaultRegisterAllocator()

-regalloc=... command line option.

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

std::optional< unsigned > getVScaleRangeMax() const

Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.

unsigned getVScaleRangeMin() const

Returns the minimum value for the vscale_range attribute.

StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

Allocate memory in an ever growing pool, as if by bump-pointer.

implements a set of functionality in the TargetMachine class for targets that make use of the indepen...

Lightweight error class with error context and mandatory checking.

FunctionPass class - This class is used to implement most global optimizations.

This pass is responsible for selecting generic machine instructions to target-specific instructions.

StringRef getABIName() const

getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

This class provides access to building LLVM's passes.

void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)

LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

This implementation is used for RISC-V ELF targets.

RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...

yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override

Allocate and return a default initialized instance of the YAML representation for the MachineFunction...

RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

void registerPassBuilderCallbacks(PassBuilder &PB) override

Allow the target to modify the pass pipeline.

bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override

Returns true if a cast between SrcAS and DestAS is a noop.

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.

bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override

Parse out the target's MachineFunctionInfo from the YAML reprsentation.

const RISCVSubtarget * getSubtargetImpl() const =delete

This pass implements the reg bank selector pass used in the GlobalISel pipeline.

RegisterPassParser class - Handle the addition of new machine passes.

RegisterRegAllocBase class - Track the registration of register allocators.

FunctionPass *(*)() FunctionPassCtor

Wrapper class representing virtual and physical registers.

Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...

Represents a range in source code.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)

Add a postprocessing step to the DAG builder.

const TargetInstrInfo * TII

Target instruction information.

const TargetRegisterInfo * TRI

Target processor register info.

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

void setMachineOutliner(bool Enable)

void setCFIFixup(bool Enable)

void setSupportsDefaultOutlining(bool Enable)

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

MCTargetOptions MCOptions

Machine level options.

Target-Independent Code Generator Pass Configuration Options.

virtual void addCodeGenPrepare()

Add pass to prepare the LLVM IR for code generation.

virtual bool addRegAssignAndRewriteFast()

Add core register allocator passes which do the actual register assignment and rewriting.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

virtual void addFastRegAlloc()

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...

virtual void addMachineSSAOptimization()

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

virtual bool addRegAssignAndRewriteOptimized()

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

A raw_ostream that writes to an SmallVector or SmallString.

Interfaces for registering analysis passes, producing common pass manager configurations,...

@ C

The default llvm calling convention, compatible with C.

ABI getTargetABI(StringRef ABIName)

static constexpr unsigned RVVBitsPerBlock

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

FunctionPass * createRISCVLandingPadSetupPass()

FunctionPass * createFastRegisterAllocator()

FastRegisterAllocation Pass - This pass register allocates as fast as possible.

FunctionPass * createRISCVPostLegalizerCombiner()

void initializeRISCVPushPopOptPass(PassRegistry &)

void initializeRISCVExpandPseudoPass(PassRegistry &)

FunctionPass * createRISCVMoveMergePass()

createRISCVMoveMergePass - returns an instance of the move merge pass.

FunctionPass * createTypePromotionLegacyPass()

Create IR Type Promotion pass.

void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)

FunctionPass * createGreedyRegisterAllocator()

Greedy register allocation pass - This pass implements a global register allocator for optimized buil...

void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)

FunctionPass * createRISCVExpandAtomicPseudoPass()

FunctionPass * createRISCVPostRAExpandPseudoPass()

Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false, bool MergeConstantByDefault=false, bool MergeConstAggressiveByDefault=false)

GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...

FunctionPass * createRISCVInsertReadWriteCSRPass()

Target & getTheRISCV32Target()

void initializeRISCVInsertVSETVLIPass(PassRegistry &)

FunctionPass * createRISCVVLOptimizerPass()

char & PostRASchedulerID

PostRAScheduler - This pass performs post register allocation scheduling.

std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)

FunctionPass * createRISCVDeadRegisterDefinitionsPass()

char & PostMachineSchedulerID

PostMachineScheduler - This pass schedules machine instructions postRA.

ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)

Create the standard converging machine scheduler.

FunctionPass * createRISCVGatherScatterLoweringPass()

FunctionPass * createRISCVMergeBaseOffsetOptPass()

Returns an instance of the Merge Base Offset Optimization pass.

char & MachineCombinerID

This pass performs instruction combining using trace metrics to estimate critical-path and resource d...

void initializeRISCVPostRAExpandPseudoPass(PassRegistry &)

CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)

Helper method for getting the code model, returning Default if CM does not have a value.

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

FunctionPass * createRISCVPreLegalizerCombiner()

char & BranchRelaxationPassID

BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...

FunctionPass * createRISCVO0PreLegalizerCombiner()

void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &)

FunctionPass * createRISCVPushPopOptimizationPass()

createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.

FunctionPass * createRISCVMakeCompressibleOptPass()

Returns an instance of the Make Compressible Optimization pass.

FunctionPass * createRISCVRedundantCopyEliminationPass()

FunctionPass * createKCFIPass()

Lowers KCFI operand bundles for indirect calls.

void initializeRISCVInsertWriteVXRMPass(PassRegistry &)

std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)

If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...

FunctionPass * createLoopDataPrefetchPass()

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)

FunctionPass * createRISCVInsertVSETVLIPass()

Returns an instance of the Insert VSETVLI pass.

CodeGenOptLevel

Code generation optimization level.

FunctionPass * createRISCVIndirectBranchTrackingPass()

FunctionPass * createRISCVOptWInstrsPass()

FunctionPass * createInterleavedAccessPass()

InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...

std::unique_ptr< ScheduleDAGMutation > createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI)

FunctionPass * createBasicRegisterAllocator()

BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...

void initializeGlobalISel(PassRegistry &)

Initialize all passes linked into the GlobalISel library.

ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)

Create a generic scheduler with no vreg liveness or DAG mutation passes.

void initializeRISCVMakeCompressibleOptPass(PassRegistry &)

FunctionPass * createRISCVCodeGenPreparePass()

char & MachinePipelinerID

This pass performs software pipelining on machine instructions.

ModulePass * createBarrierNoopPass()

createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.

void initializeRISCVVLOptimizerPass(PassRegistry &)

std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)

If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...

void initializeRISCVOptWInstrsPass(PassRegistry &)

FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)

void initializeRISCVCodeGenPreparePass(PassRegistry &)

Target & getTheRISCV64Target()

FunctionPass * createRISCVVectorPeepholePass()

void call_once(once_flag &flag, Function &&F, Args &&... ArgList)

Execute the function specified as a parameter once.

void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)

void initializeKCFIPass(PassRegistry &)

void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)

FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)

FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)

void initializeRISCVGatherScatterLoweringPass(PassRegistry &)

FunctionPass * createRISCVExpandPseudoPass()

FunctionPass * createRISCVPreRAExpandPseudoPass()

FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

T bit_floor(T Value)

Returns the largest integral power of two no greater than Value if Value is nonzero.

FunctionPass * createRISCVInsertWriteVXRMPass()

MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)

void initializeRISCVVectorPeepholePass(PassRegistry &)

FunctionPass * createRISCVZacasABIFixPass()

void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)

void initializeRISCVPostLegalizerCombinerPass(PassRegistry &)

void initializeRISCVMoveMergePass(PassRegistry &)

Implement std::hash so that hash_code can be used in STL containers.

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

static bool isRVVRegClass(const TargetRegisterClass *RC)

RegisterTargetMachine - Helper template for registering a target machine implementation,...

The llvm::once_flag structure.

Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.