LLVM: lib/Target/RISCV/RISCVTargetMachine.cpp File Reference (original) (raw)

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Macros
#define GET_PASS_REGISTRY "RISCVPassRegistry.def"
#define ADD_CLASS_PASS_TO_PASS_NAME(NAME, CREATE_PASS)
#define ADD_CLASS_PASS_TO_PASS_NAME_WITH_PARAMS(NAME, CLASS)
#define MODULE_ANALYSIS(NAME, CREATE_PASS)
#define MODULE_PASS(NAME, CREATE_PASS)
#define MODULE_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
#define FUNCTION_ANALYSIS(NAME, CREATE_PASS)
#define FUNCTION_ALIAS_ANALYSIS(NAME, CREATE_PASS)
#define FUNCTION_PASS(NAME, CREATE_PASS)
#define FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
#define LOOP_ANALYSIS(NAME, CREATE_PASS)
#define LOOP_PASS(NAME, CREATE_PASS)
#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS)
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
#define MACHINE_FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
#define ADD_PASS(NAME, CREATE_PASS)
#define ADD_PASS_WITH_PARAMS(NAME, CREATE_PASS, PARSER)
#define MODULE_PASS(NAME, CREATE_PASS)
#define MODULE_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
#define FUNCTION_PASS(NAME, CREATE_PASS)
#define FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
#define LOOP_PASS(NAME, CREATE_PASS)
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
#define MACHINE_FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, PARAMS)
#define MODULE_ANALYSIS(NAME, CREATE_PASS)
#define FUNCTION_ANALYSIS(NAME, CREATE_PASS)
#define FUNCTION_ALIAS_ANALYSIS(NAME, CREATE_PASS)
#define LOOP_ANALYSIS(NAME, CREATE_PASS)
#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS)
Variables
static cl::opt< bool > EnableRedundantCopyElimination ("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge ("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool > EnableMachineCombiner ("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > RVVVectorBitsMaxOpt ("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt ("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static cl::opt< bool > EnableRISCVCopyPropagation ("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRISCVDeadRegisterElimination ("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool > EnableSinkFold ("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch ("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< bool > DisableVectorMaskMutation ("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableMachinePipeliner ("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableCFIInstrInserter ("riscv-enable-cfi-instr-inserter", cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false), cl::Hidden)

◆ ADD_CLASS_PASS_TO_PASS_NAME

#define ADD_CLASS_PASS_TO_PASS_NAME ( NAME,
CREATE_PASS )

Value:

PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME);

PassInstrumentationCallbacks PIC

◆ ADD_CLASS_PASS_TO_PASS_NAME_WITH_PARAMS

#define ADD_CLASS_PASS_TO_PASS_NAME_WITH_PARAMS ( NAME,
CLASS )

Value:

PIC->addClassToPassName(CLASS, NAME);

◆ ADD_PASS

#define ADD_PASS ( NAME,
CREATE_PASS )

Value:

if (Name == NAME) { \

PM.addPass(CREATE_PASS); \

return true; \

}

◆ ADD_PASS_WITH_PARAMS

#define ADD_PASS_WITH_PARAMS ( NAME,
CREATE_PASS,
PARSER )

Value:

if (!Params) { \

errs() << NAME ": " << toString(Params.takeError()) << '\n'; \

return false; \

} \

PM.addPass(CREATE_PASS(Params.get())); \

return true; \

}

static bool checkParametrizedPassName(StringRef Name, StringRef PassName)

static auto parsePassParameters(ParametersParseCallableT &&Parser, StringRef Name, StringRef PassName) -> decltype(Parser(StringRef{}))

This performs customized parsing of pass name with parameters.

std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)

◆ FUNCTION_ALIAS_ANALYSIS [1/2]

#define FUNCTION_ALIAS_ANALYSIS ( NAME,
CREATE_PASS )

Value:

#define ADD_CLASS_PASS_TO_PASS_NAME(NAME, CREATE_PASS)

◆ FUNCTION_ALIAS_ANALYSIS [2/2]

#define FUNCTION_ALIAS_ANALYSIS ( NAME,
CREATE_PASS )

Value:

if (Name == NAME) { \

AM.registerFunctionAnalysis< \

std::remove_reference_t<decltype(CREATE_PASS)>>(); \

return true; \

}

◆ FUNCTION_ANALYSIS [1/2]

#define FUNCTION_ANALYSIS ( NAME,
CREATE_PASS )

◆ FUNCTION_ANALYSIS [2/2]

#define FUNCTION_ANALYSIS ( NAME,
CREATE_PASS )

Value:

AM.registerPass([&] { return CREATE_PASS; });

◆ FUNCTION_PASS [1/2]

#define FUNCTION_PASS ( NAME,
CREATE_PASS )

◆ FUNCTION_PASS [2/2]

#define FUNCTION_PASS ( NAME,
CREATE_PASS )

Value:

#define ADD_PASS(NAME, CREATE_PASS)

◆ FUNCTION_PASS_WITH_PARAMS [1/2]

#define FUNCTION_PASS_WITH_PARAMS ( NAME,
CLASS,
CREATE_PASS,
PARSER,
PARAMS )

Value:

#define ADD_CLASS_PASS_TO_PASS_NAME_WITH_PARAMS(NAME, CLASS)

◆ FUNCTION_PASS_WITH_PARAMS [2/2]

#define FUNCTION_PASS_WITH_PARAMS ( NAME,
CLASS,
CREATE_PASS,
PARSER,
PARAMS )

Value:

#define ADD_PASS_WITH_PARAMS(NAME, CREATE_PASS, PARSER)

◆ GET_PASS_REGISTRY

#define GET_PASS_REGISTRY "RISCVPassRegistry.def"

◆ LOOP_ANALYSIS [1/2]

#define LOOP_ANALYSIS ( NAME,
CREATE_PASS )

◆ LOOP_ANALYSIS [2/2]

#define LOOP_ANALYSIS ( NAME,
CREATE_PASS )

Value:

AM.registerPass([&] { return CREATE_PASS; });

◆ LOOP_PASS [1/2]

#define LOOP_PASS ( NAME,
CREATE_PASS )

◆ LOOP_PASS [2/2]

#define LOOP_PASS ( NAME,
CREATE_PASS )

◆ MACHINE_FUNCTION_ANALYSIS [1/2]

#define MACHINE_FUNCTION_ANALYSIS ( NAME,
CREATE_PASS )

◆ MACHINE_FUNCTION_ANALYSIS [2/2]

#define MACHINE_FUNCTION_ANALYSIS ( NAME,
CREATE_PASS )

Value:

AM.registerPass([&] { return CREATE_PASS; });

◆ MACHINE_FUNCTION_PASS [1/2]

#define MACHINE_FUNCTION_PASS ( NAME,
CREATE_PASS )

◆ MACHINE_FUNCTION_PASS [2/2]

#define MACHINE_FUNCTION_PASS ( NAME,
CREATE_PASS )

◆ MACHINE_FUNCTION_PASS_WITH_PARAMS [1/2]

#define MACHINE_FUNCTION_PASS_WITH_PARAMS ( NAME,
CLASS,
CREATE_PASS,
PARSER,
PARAMS )

◆ MACHINE_FUNCTION_PASS_WITH_PARAMS [2/2]

#define MACHINE_FUNCTION_PASS_WITH_PARAMS ( NAME,
CLASS,
CREATE_PASS,
PARSER,
PARAMS )

◆ MODULE_ANALYSIS [1/2]

#define MODULE_ANALYSIS ( NAME,
CREATE_PASS )

◆ MODULE_ANALYSIS [2/2]

#define MODULE_ANALYSIS ( NAME,
CREATE_PASS )

Value:

AM.registerPass([&] { return CREATE_PASS; });

◆ MODULE_PASS [1/2]

#define MODULE_PASS ( NAME,
CREATE_PASS )

◆ MODULE_PASS [2/2]

#define MODULE_PASS ( NAME,
CREATE_PASS )

◆ MODULE_PASS_WITH_PARAMS [1/2]

#define MODULE_PASS_WITH_PARAMS ( NAME,
CLASS,
CREATE_PASS,
PARSER,
PARAMS )

◆ MODULE_PASS_WITH_PARAMS [2/2]

#define MODULE_PASS_WITH_PARAMS ( NAME,
CLASS,
CREATE_PASS,
PARSER,
PARAMS )

◆ getEffectiveRelocModel()

◆ LLVMInitializeRISCVTarget()

Definition at line 111 of file RISCVTargetMachine.cpp.

References A(), B(), llvm::PassRegistry::getPassRegistry(), llvm::getTheRISCV32beTarget(), llvm::getTheRISCV32Target(), llvm::getTheRISCV64beTarget(), llvm::getTheRISCV64Target(), llvm::initializeGlobalISel(), llvm::initializeKCFIPass(), llvm::initializeRISCVAsmPrinterPass(), llvm::initializeRISCVCodeGenPrepareLegacyPassPass(), llvm::initializeRISCVDAGToDAGISelLegacyPass(), llvm::initializeRISCVDeadRegisterDefinitionsPass(), llvm::initializeRISCVExpandAtomicPseudoPass(), llvm::initializeRISCVExpandPseudoPass(), llvm::initializeRISCVFoldMemOffsetPass(), llvm::initializeRISCVGatherScatterLoweringPass(), llvm::initializeRISCVIndirectBranchTrackingPass(), llvm::initializeRISCVInsertReadWriteCSRPass(), llvm::initializeRISCVInsertVSETVLIPass(), llvm::initializeRISCVInsertWriteVXRMPass(), llvm::initializeRISCVLateBranchOptPass(), llvm::initializeRISCVLoadStoreOptPass(), llvm::initializeRISCVMakeCompressibleOptPass(), llvm::initializeRISCVMergeBaseOffsetOptPass(), llvm::initializeRISCVMoveMergePass(), llvm::initializeRISCVO0PreLegalizerCombinerPass(), llvm::initializeRISCVOptWInstrsPass(), llvm::initializeRISCVPostLegalizerCombinerPass(), llvm::initializeRISCVPostRAExpandPseudoPass(), llvm::initializeRISCVPreAllocZilsdOptPass(), llvm::initializeRISCVPreLegalizerCombinerPass(), llvm::initializeRISCVPreRAExpandPseudoPass(), llvm::initializeRISCVPromoteConstantPass(), llvm::initializeRISCVPushPopOptPass(), llvm::initializeRISCVRedundantCopyEliminationPass(), llvm::initializeRISCVVectorPeepholePass(), llvm::initializeRISCVVLOptimizerPass(), llvm::initializeRISCVVMV0EliminationPass(), LLVM_ABI, LLVM_EXTERNAL_VISIBILITY, X, and Y.

◆ DisableVectorMaskMutation

cl::opt< bool > DisableVectorMaskMutation("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden) ( "riscv-disable-vector-mask-mutation" , cl::desc("Disable the vector mask scheduling mutation") , cl::init(false) , cl::Hidden ) static

◆ EnableCFIInstrInserter

◆ EnableGlobalMerge

◆ EnableLoopDataPrefetch

◆ EnableMachineCombiner

cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden) ( "riscv-enable-machine-combiner" , cl::desc("Enable the machine combiner pass") , cl::init(true) , cl::Hidden ) static

◆ EnableMachinePipeliner

cl::opt< bool > EnableMachinePipeliner("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden) ( "riscv-enable-pipeliner" , cl::desc("Enable Machine Pipeliner for RISC-V") , cl::init(false) , cl::Hidden ) static

◆ EnableRedundantCopyElimination

cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden) ( "riscv-enable-copyelim" , cl::desc("Enable the redundant copy elimination pass") , cl::init(true) , cl::Hidden ) static

◆ EnableRISCVCopyPropagation

cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden) ( "riscv-enable-copy-propagation" , cl::desc("Enable the copy propagation with RISC-V copy instr") , cl::init(true) , cl::Hidden ) static

◆ EnableRISCVDeadRegisterElimination

cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0"), cl::init(true)) ( "riscv-enable-dead-defs" , cl::Hidden , cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0") , cl::init(true) ) static

◆ EnableSinkFold

cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden) ( "riscv-enable-sink-fold" , cl::desc("Enable sinking and folding of instruction copies") , cl::init(true) , cl::Hidden ) static

◆ RVVVectorBitsMaxOpt

cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden) ( "riscv-v-vector-bits-max" , cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed.") , cl::init(0) , cl::Hidden ) static

◆ RVVVectorBitsMinOpt

cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden) ( "riscv-v-vector-bits-min" , cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors.") , cl::init(-1) , cl::Hidden ) static