LLVM: lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp Source File (original) (raw)
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42#define DEBUG_TYPE "machine-scheduler"
43
44namespace llvm {
45
47 return MI.isFullCopy() && MI.getOperand(0).getReg() == RISCV::V0 &&
48 MI.getOperand(1).getReg().isVirtual();
49}
50
52 if (SU.Succs.size() != 1)
53 return false;
55
57 return false;
58
61 return false;
63}
64
66private:
68
69public:
71
73 SUnit *NearestUseV0SU = nullptr;
77 bool UseV0 = MI->findRegisterUseOperand(RISCV::V0, TRI);
80
81 if (UseV0) {
82 NearestUseV0SU = &SU;
83
84
85 if (DefMask.size() > 1 && ->isCopy()) {
86 for (SUnit *Def : DefMask)
89 }
90
91 if (!DefMask.empty())
93 }
94
95 if (NearestUseV0SU && NearestUseV0SU != &SU && isSoleUseCopyToV0(SU) &&
96
97
98
101 }
102 }
103};
104
105std::unique_ptr
107 return std::make_unique(TRI);
108}
109
110}
Register const TargetRegisterInfo * TRI
Representation of each machine instruction.
RISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI)
Definition RISCVVectorMaskDAGMutation.cpp:70
void apply(ScheduleDAGInstrs *DAG) override
Definition RISCVVectorMaskDAGMutation.cpp:72
bool isWeak() const
Tests if this a weak dependence.
@ Artificial
Arbitrary strong DAG edge (no real dependence).
Scheduling unit. This is a node in the scheduling DAG.
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
SmallVector< SDep, 4 > Succs
All sunit successors.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
A ScheduleDAG for scheduling lists of MachineInstr.
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
bool canAddEdge(SUnit *SuccSU, SUnit *PredSU)
True if an edge can be added from PredSU to SuccSU without creating a cycle.
Mutate the DAG as a postpass after normal DAG building.
std::vector< SUnit > SUnits
The scheduling units.
iterator erase(const_iterator CI)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static RISCVVType::VLMUL getLMul(uint64_t TSFlags)
This is an optimization pass for GlobalISel generic memory operations.
std::unique_ptr< ScheduleDAGMutation > createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI)
Definition RISCVVectorMaskDAGMutation.cpp:106
static bool isCopyToV0(const MachineInstr &MI)
Definition RISCVVectorMaskDAGMutation.cpp:46
static bool isSoleUseCopyToV0(SUnit &SU)
Definition RISCVVectorMaskDAGMutation.cpp:51