ReachingDefAnalysis.cpp Source File (original) (raw)

19using namespace llvm;

21#define DEBUG_TYPE "reaching-defs-analysis"

29 RDI.run(MF);

30 return RDI;

31}

39 OS << "Reaching definitions for for machine function: " << MF.getName()

40 << '\n';

41 RDI.print(OS);

43}

46 "Reaching Definitions Analysis", false, true)

53}

61 MachineFunctionAnalysisManager::Invalidator &) {

65 return !PAC.preserved() &&

68}

105

108 int DefFrameIndex = 0;

109 int SrcFrameIndex = 0;

110 if (TII->isStoreToStackSlot(MI, DefFrameIndex) ||

111 TII->isStackSlotCopy(MI, DefFrameIndex, SrcFrameIndex))

112 return DefFrameIndex == FrameIndex;

113 return false;

114}

115

118 assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&

119 "Unexpected basic block number.");

120 MBBReachingDefs.startBasicBlock(MBBNumber, NumRegUnits);

121

122

123 CurInstr = 0;

124

125

126

127 if (LiveRegs.empty())

128 LiveRegs.assign(NumRegUnits, ReachingDefDefaultVal);

129

130

132 for (const auto &LI : MBB->liveins()) {

133 for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {

134

135

136

137 if (LiveRegs[static_cast<unsigned>(Unit)] != -1) {

138 LiveRegs[static_cast<unsigned>(Unit)] = -1;

139 MBBReachingDefs.append(MBBNumber, Unit, -1);

140 }

141 }

142 }

144 return;

145 }

146

147

149 assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&

150 "Should have pre-allocated MBBInfos for all MBBs");

151 const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];

152

153

154 if (Incoming.empty())

155 continue;

156

157

158 for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit)

159 LiveRegs[Unit] = std::max(LiveRegs[Unit], Incoming[Unit]);

160 }

161

162

163 for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit)

164 if (LiveRegs[Unit] != ReachingDefDefaultVal)

165 MBBReachingDefs.append(MBBNumber, static_cast<MCRegUnit>(Unit),

166 LiveRegs[Unit]);

167}

168

170 assert(!LiveRegs.empty() && "Must enter basic block first.");

172 assert(MBBNumber < MBBOutRegsInfos.size() &&

173 "Unexpected basic block number.");

174

175 MBBOutRegsInfos[MBBNumber] = LiveRegs;

176

177

178

179

180

181 for (int &OutLiveReg : MBBOutRegsInfos[MBBNumber])

182 if (OutLiveReg != ReachingDefDefaultVal)

183 OutLiveReg -= CurInstr;

184 LiveRegs.clear();

185}

186

188 assert(->isDebugInstr() && "Won't process debug instructions");

189

190 unsigned MBBNumber = MI->getParent()->getNumber();

191 assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&

192 "Unexpected basic block number.");

193

194 for (auto &MO : MI->operands()) {

195 if (MO.isFI()) {

197 if ( isFIDef (*MI, FrameIndex, TII))

198 continue;

199 MBBFrameObjsReachingDefs[{MBBNumber, FrameIndex}].push_back(CurInstr);

200 }

202 continue;

203 for (MCRegUnit Unit : TRI->regunits(MO.getReg().asMCReg())) {

204

206 << *MI);

207

208

209 if (LiveRegs[static_cast<unsigned>(Unit)] != CurInstr) {

210 LiveRegs[static_cast<unsigned>(Unit)] = CurInstr;

211 MBBReachingDefs.append(MBBNumber, Unit, CurInstr);

212 }

213 }

214 }

215 InstIds[MI] = CurInstr;

216 ++CurInstr;

217}

218

221 assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&

222 "Unexpected basic block number.");

223

224

225 auto NonDbgInsts =

227 int NumInsts = std::distance(NonDbgInsts.begin(), NonDbgInsts.end());

228

229

230

232 assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() &&

233 "Should have pre-allocated MBBInfos for all MBBs");

234 const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()];

235

236 if (Incoming.empty())

237 continue;

238

239 for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {

240 int Def = Incoming[Unit];

241 if (Def == ReachingDefDefaultVal)

242 continue;

243

244 auto Defs = MBBReachingDefs.defs(MBBNumber, static_cast<MCRegUnit>(Unit));

245 if (!Defs.empty() && Defs.front() < 0) {

246 if (Defs.front() >= Def)

247 continue;

248

249

250 MBBReachingDefs.replaceFront(MBBNumber, static_cast<MCRegUnit>(Unit),

251 Def);

252 } else {

253

254 MBBReachingDefs.prepend(MBBNumber, static_cast<MCRegUnit>(Unit), Def);

255 }

256

257

258

259 if (MBBOutRegsInfos[MBBNumber][Unit] < Def - NumInsts)

260 MBBOutRegsInfos[MBBNumber][Unit] = Def - NumInsts;

261 }

262 }

263}

264

265void ReachingDefInfo::processBasicBlock(

267 MachineBasicBlock *MBB = TraversedMBB.MBB;

269 << (!TraversedMBB.IsDone ? ": incomplete\n"

270 : ": all preds known\n"));

271

273

274 reprocessBasicBlock(MBB);

275 return;

276 }

277

278 enterBasicBlock(MBB);

279 for (MachineInstr &MI :

281 processDefs(&MI);

282 leaveBasicBlock(MBB);

283}

284

286 MF = &mf;

290 LLVM_DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");

293}

294

296 OS << "RDA results for " << MF->getName() << "\n";

297 int Num = 0;

304 if (MO.isFI()) {

305 int FrameIndex = MO.getIndex();

307 } else if (MO.isReg()) {

308 if (MO.isDef())

309 continue;

310 Reg = MO.getReg();

311 if (!Reg.isValid())

312 continue;

313 } else

314 continue;

317 MO.print(OS, TRI);

320 Nums.push_back(InstToNumMap[Def]);

322 OS << ":{ ";

323 for (int Num : Nums)

324 OS << Num << " ";

325 OS << "}\n";

326 }

327 OS << Num << ": " << MI << "\n";

328 InstToNumMap[&MI] = Num;

329 ++Num;

330 }

331 }

332}

333

335 RDI.run(mf);

336 return false;

337}

338

340

341 MBBOutRegsInfos.clear();

342 MBBReachingDefs.clear();

343 MBBFrameObjsReachingDefs.clear();

344 InstIds.clear();

345 LiveRegs.clear();

346}

347

353

355 NumRegUnits = TRI->getNumRegUnits();

356 NumStackObjects = MF->getFrameInfo().getNumObjects();

357 ObjectIndexBegin = MF->getFrameInfo().getObjectIndexBegin();

358 MBBReachingDefs.init(MF->getNumBlockIDs());

359

360 MBBOutRegsInfos.resize(MF->getNumBlockIDs());

362 TraversedMBBOrder = Traversal.traverse(*MF);

363}

364

366

368 processBasicBlock(TraversedMBB);

369#ifndef NDEBUG

370

371 for (unsigned MBBNumber = 0, NumBlockIDs = MF->getNumBlockIDs();

372 MBBNumber != NumBlockIDs; ++MBBNumber) {

373 for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {

374 int LastDef = ReachingDefDefaultVal;

375 for (int Def :

376 MBBReachingDefs.defs(MBBNumber, static_cast<MCRegUnit>(Unit))) {

377 assert(Def > LastDef && "Defs must be sorted and unique");

378 LastDef = Def;

379 }

380 }

381 }

382#endif

383}

384

386 assert(InstIds.count(MI) && "Unexpected machine instuction.");

387 int InstId = InstIds.lookup(MI);

388 int DefRes = ReachingDefDefaultVal;

389 unsigned MBBNumber = MI->getParent()->getNumber();

390 assert(MBBNumber < MBBReachingDefs.numBlockIDs() &&

391 "Unexpected basic block number.");

392 int LatestDef = ReachingDefDefaultVal;

393

394 if (Reg.isStack()) {

395

396 int FrameIndex = Reg.stackSlotIndex();

397 auto Lookup = MBBFrameObjsReachingDefs.find({MBBNumber, FrameIndex});

398 if (Lookup == MBBFrameObjsReachingDefs.end())

399 return LatestDef;

400 auto &Defs = Lookup->second;

401 for (int Def : Defs) {

402 if (Def >= InstId)

403 break;

404 DefRes = Def;

405 }

406 LatestDef = std::max(LatestDef, DefRes);

407 return LatestDef;

408 }

409

410 for (MCRegUnit Unit : TRI->regunits(Reg)) {

411 for (int Def : MBBReachingDefs.defs(MBBNumber, Unit)) {

412 if (Def >= InstId)

413 break;

414 DefRes = Def;

415 }

416 LatestDef = std::max(LatestDef, DefRes);

417 }

418 return LatestDef;

419}

420

425 : nullptr;

426}

427

432 if (ParentA != ParentB)

433 return false;

434

436}

437

439 int InstId) const {

440 assert(static_cast<size_t>(MBB->getNumber()) <

442 "Unexpected basic block number.");

443 assert(InstId < static_cast<int>(MBB->size()) &&

444 "Unexpected instruction id.");

445

446 if (InstId < 0)

447 return nullptr;

448

449 for (auto &MI : *MBB) {

450 auto F = InstIds.find(&MI);

451 if (F != InstIds.end() && F->second == InstId)

452 return &MI;

453 }

454

455 return nullptr;

456}

457

459 assert(InstIds.count(MI) && "Unexpected machine instuction.");

461}

462

466

468 InstSet &Uses) const {

471 while (++MI != MBB->end()) {

472 if (MI->isDebugInstr())

473 continue;

474

475

476

477 if (getReachingLocalMIDef(&*MI, Reg) != Def)

478 return;

479

480 for (auto &MO : MI->operands()) {

482 continue;

483

485 if (MO.isKill())

486 return;

487 }

488 }

489}

490

492 InstSet &Uses) const {

495 for (auto &MO : MI.operands()) {

497 continue;

499 return false;

501 }

502 }

503 auto Last = MBB->getLastNonDebugInstr();

505 return true;

507}

508

510 InstSet &Uses) const {

512

513

515

516

518 if (LiveOut != MI)

519 return;

520

523 while (!ToVisit.empty()) {

525 if (Visited.count(MBB) || MBB ->isLiveIn(Reg))

526 continue;

530 }

531 }

532}

533

535 InstSet &Defs) const {

538 return;

539 }

540

541 for (auto *MBB : MI->getParent()->predecessors())

543}

544

546 InstSet &Defs) const {

549}

550

552 InstSet &Defs, BlockSet &VisitedBBs) const {

554 return;

555

558 LiveRegs.addLiveOuts(*MBB);

559 if (Reg.isPhysical() && LiveRegs.available(Reg))

560 return;

561

564 else

565 for (auto *Pred : MBB->predecessors())

566 getLiveOuts(Pred, Reg, Defs, VisitedBBs);

567}

568

571

572 MachineInstr *LocalDef = getReachingLocalMIDef(MI, Reg);

573 if (LocalDef && InstIds.lookup(LocalDef) < InstIds.lookup(MI))

574 return LocalDef;

575

580

581

582

583

584 if (Incoming.size() == 1 && (*Incoming.begin())->getParent() != Parent)

586 return nullptr;

587}

588

590 unsigned Idx) const {

591 assert(MI->getOperand(Idx).isReg() && "Expected register operand");

593}

594

597 assert(MO.isReg() && "Expected register operand");

599}

600

604 LiveRegs.addLiveOuts(*MBB);

605

606

607 if (!LiveRegs.available(Reg))

608 return true;

609

610

611

614 LiveRegs.stepBackward(Last);

615 if (!LiveRegs.available(Reg))

616 return InstIds.lookup(&Last) > InstIds.lookup(MI);

617 }

618 return false;

619}

620

623 auto Last = MBB->getLastNonDebugInstr();

624 if (Last != MBB->end() &&

626 return true;

627

629 return Def == getReachingLocalMIDef(MI, Reg);

630

631 return false;

632}

633

638 LiveRegs.addLiveOuts(*MBB);

639 if (Reg.isPhysical() && LiveRegs.available(Reg))

640 return false;

641

642 auto Last = MBB->getLastNonDebugInstr();

645 return false;

646

647

648 for (auto &MO : Last->operands())

650 return false;

651

652 return true;

653}

654

658 LiveRegs.addLiveOuts(*MBB);

659 if (Reg.isPhysical() && LiveRegs.available(Reg))

660 return nullptr;

661

662 auto Last = MBB->getLastNonDebugInstr();

664 return nullptr;

665

666 if (Reg.isStack()) {

667 int FrameIndex = Reg.stackSlotIndex();

669 return &*Last;

670 }

671

673

674 for (auto &MO : Last->operands())

676 return &*Last;

677

678 return Def < 0 ? nullptr : getInstFromId(MBB, Def);

679}

680

682 return MI.mayLoadOrStore() || MI.mayRaiseFPException() ||

683 MI.hasUnmodeledSideEffects() || MI.isTerminator() ||

684 MI.isCall() || MI.isBarrier() || MI.isBranch() || MI.isReturn();

685}

686

687

688

689

690template

693 return false;

694

695 SmallSet<Register, 2> Defs;

696

697 for (auto &MO : From->operands()) {

699 continue;

700 if (MO.isDef())

701 Defs.insert(MO.getReg());

703 return false;

704 }

705

706

707

708

709 for (auto I = ++Iterator(From), E = Iterator(To); I != E; ++I) {

711 return false;

712 for (auto &MO : I->operands())

713 if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg()))

714 return false;

715 }

716 return true;

717}

718

722

723 for (auto I = Iterator(From), E = From->getParent()->end(); I != E; ++I)

724 if (&*I == To)

725 return isSafeToMove(From, To);

726 return false;

727}

728

732

733 for (auto I = Iterator(From), E = From->getParent()->rend(); I != E; ++I)

734 if (&*I == To)

735 return isSafeToMove(From, To);

736 return false;

737}

738

745

747 InstSet &Ignore) const {

750}

751

754 if (Visited.count(MI) || Ignore.count(MI))

755 return true;

757

758

759 return false;

760 }

761

762 Visited.insert(MI);

763 for (auto &MO : MI->operands()) {

765 continue;

766

769

770 for (auto *I : Uses) {

772 continue;

774 return false;

775 }

776 }

778 return true;

779}

780

782 InstSet &Dead) const {

783 Dead.insert(MI);

786 return false;

787

788 unsigned LiveDefs = 0;

789 for (auto &MO : Def->operands()) {

791 continue;

792 if (!MO.isDead())

793 ++LiveDefs;

794 }

795

796 if (LiveDefs > 1)

797 return false;

798

802 };

803

804 for (auto &MO : MI->operands()) {

806 continue;

808 if (IsDead(Def, MO.getReg()))

810 }

811}

812

817

819 InstSet &Ignore) const {

820

822 if (auto *Def = getReachingLocalMIDef(MI, Reg)) {

826 return false;

827 } else

828 return false;

829 }

830

832

835 for (auto E = MBB->end(); I != E; ++I) {

837 continue;

838 for (auto &MO : I->operands())

840 return false;

841 }

842 }

843 return true;

844}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

ReachingDefInfo InstSet InstSet & Ignore

ReachingDefInfo InstSet & ToRemove

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

static bool isValidRegUseOf(const MachineOperand &MO, Register Reg, const TargetRegisterInfo *TRI)

Definition ReachingDefAnalysis.cpp:88

static bool mayHaveSideEffects(MachineInstr &MI)

Definition ReachingDefAnalysis.cpp:681

static bool isValidReg(const MachineOperand &MO)

Definition ReachingDefAnalysis.cpp:80

static bool isFIDef(const MachineInstr &MI, int FrameIndex, const TargetInstrInfo *TII)

Definition ReachingDefAnalysis.cpp:106

static bool isValidRegDef(const MachineOperand &MO)

Definition ReachingDefAnalysis.cpp:95

static bool isValidRegDefOf(const MachineOperand &MO, Register Reg, const TargetRegisterInfo *TRI)

Definition ReachingDefAnalysis.cpp:99

static bool isValidRegUse(const MachineOperand &MO)

Definition ReachingDefAnalysis.cpp:84

Remove Loads Into Fake Uses

This file defines generic set operations that may be used on set's of different types,...

This file defines the SmallSet class.

static int Lookup(ArrayRef< TableEntry > Table, unsigned Opcode)

This templated class represents "all analyses that operate over " (e....

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

void setPreservesAll()

Set by analyses that do not transform their input at all.

Represents analyses that only rely on functions' control flow.

A set of register units used to track register liveness.

This class provides the basic blocks traversal order used by passes like ReachingDefAnalysis and Exec...

TraversalOrder traverse(MachineFunction &MF)

unsigned numBlockIDs() const

An RAII based helper class to modify MachineFunctionProperties when running pass.

instr_iterator instr_begin()

iterator_range< livein_iterator > liveins() const

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

MachineInstrBundleIterator< MachineInstr, true > reverse_iterator

instr_iterator instr_end()

iterator_range< pred_iterator > predecessors()

MachineInstrBundleIterator< MachineInstr > iterator

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Properties which a MachineFunction may have at a given point in time.

StringRef getName() const

getName - Return the name of the corresponding LLVM function.

Representation of each machine instruction.

const MachineBasicBlock * getParent() const

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

PreservedAnalysisChecker getChecker() const

Build a checker for this PreservedAnalyses and the specified analysis type.

Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition ReachingDefAnalysis.cpp:26

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Definition ReachingDefAnalysis.cpp:70

bool runOnMachineFunction(MachineFunction &F) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

Definition ReachingDefAnalysis.cpp:334

MachineFunctionProperties getRequiredProperties() const override

Definition ReachingDefAnalysis.cpp:76

This class provides the reaching def analysis.

MachineInstr * getUniqueReachingMIDef(MachineInstr *MI, Register Reg) const

If a single MachineInstr creates the reaching definition, then return it.

Definition ReachingDefAnalysis.cpp:569

bool isReachingDefLiveOut(MachineInstr *MI, Register Reg) const

Return whether the reaching def for MI also is live out of its parent block.

Definition ReachingDefAnalysis.cpp:634

bool isSafeToMoveForwards(MachineInstr *From, MachineInstr *To) const

Return whether From can be moved forwards to just before To.

Definition ReachingDefAnalysis.cpp:719

int getReachingDef(MachineInstr *MI, Register Reg) const

Provides the instruction id of the closest reaching def instruction of Reg that reaches MI,...

Definition ReachingDefAnalysis.cpp:385

void run(MachineFunction &mf)

Definition ReachingDefAnalysis.cpp:285

void getReachingLocalUses(MachineInstr *MI, Register Reg, InstSet &Uses) const

Provides the uses, in the same block as MI, of register that MI defines.

Definition ReachingDefAnalysis.cpp:467

int getClearance(MachineInstr *MI, Register Reg) const

Provides the clearance - the number of instructions since the closest reaching def instuction of Reg ...

Definition ReachingDefAnalysis.cpp:458

bool isRegDefinedAfter(MachineInstr *MI, Register Reg) const

Return whether the given register is defined after MI.

Definition ReachingDefAnalysis.cpp:621

void init()

Initialize data structures.

Definition ReachingDefAnalysis.cpp:354

void print(raw_ostream &OS)

Definition ReachingDefAnalysis.cpp:295

bool hasLocalDefBefore(MachineInstr *MI, Register Reg) const

Provide whether the register has been defined in the same basic block as, and before,...

Definition ReachingDefAnalysis.cpp:463

void reset()

Re-run the analysis.

Definition ReachingDefAnalysis.cpp:348

void getGlobalUses(MachineInstr *MI, Register Reg, InstSet &Uses) const

Collect the users of the value stored in Reg, which is defined by MI.

Definition ReachingDefAnalysis.cpp:509

void releaseMemory()

Definition ReachingDefAnalysis.cpp:339

MachineInstr * getMIOperand(MachineInstr *MI, unsigned Idx) const

If a single MachineInstr creates the reaching definition, for MIs operand at Idx, then return it.

Definition ReachingDefAnalysis.cpp:589

void getLiveOuts(MachineBasicBlock *MBB, Register Reg, InstSet &Defs, BlockSet &VisitedBBs) const

Search MBB for a definition of Reg and insert it into Defs.

Definition ReachingDefAnalysis.cpp:551

void traverse()

Traverse the machine function, mapping definitions.

Definition ReachingDefAnalysis.cpp:365

bool isSafeToMoveBackwards(MachineInstr *From, MachineInstr *To) const

Return whether From can be moved backwards to just after To.

Definition ReachingDefAnalysis.cpp:729

void collectKilledOperands(MachineInstr *MI, InstSet &Dead) const

Assuming MI is dead, recursively search the incoming operands which are killed by MI and collect thos...

Definition ReachingDefAnalysis.cpp:781

bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, Register Reg) const

Return whether A and B use the same def of Reg.

Definition ReachingDefAnalysis.cpp:428

bool isRegUsedAfter(MachineInstr *MI, Register Reg) const

Return whether the given register is used after MI, whether it's a local use or a live out.

Definition ReachingDefAnalysis.cpp:601

void getGlobalReachingDefs(MachineInstr *MI, Register Reg, InstSet &Defs) const

Collect all possible definitions of the value stored in Reg, which is used by MI.

Definition ReachingDefAnalysis.cpp:534

bool isSafeToRemove(MachineInstr *MI, InstSet &ToRemove) const

Return whether removing this instruction will have no effect on the program, returning the redundant ...

Definition ReachingDefAnalysis.cpp:739

MachineInstr * getLocalLiveOutMIDef(MachineBasicBlock *MBB, Register Reg) const

Return the local MI that produces the live out value for Reg, or nullptr for a non-live out or non-lo...

Definition ReachingDefAnalysis.cpp:655

bool invalidate(MachineFunction &F, const PreservedAnalyses &PA, MachineFunctionAnalysisManager::Invalidator &)

Handle invalidation explicitly.

Definition ReachingDefAnalysis.cpp:59

bool getLiveInUses(MachineBasicBlock *MBB, Register Reg, InstSet &Uses) const

For the given block, collect the instructions that use the live-in value of the provided register.

Definition ReachingDefAnalysis.cpp:491

bool isSafeToDefRegAt(MachineInstr *MI, Register Reg) const

Return whether a MachineInstr could be inserted at MI and safely define the given register without af...

Definition ReachingDefAnalysis.cpp:813

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition ReachingDefAnalysis.cpp:34

Wrapper class representing virtual and physical registers.

static Register index2StackSlot(int FI)

Convert a non-negative frame index to a stack slot register value.

size_type count(ConstPtrType Ptr) const

count - Return 1 if the specified pointer is in the set, 0 otherwise.

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

size_type count(const T &V) const

count - Return 1 if the element is in the set, 0 otherwise.

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

This class implements an extremely fast bulk output stream that can only output to a stream.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

NodeAddr< DefNode * > Def

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI void initializeReachingDefInfoWrapperPassPass(PassRegistry &)

bool set_is_subset(const S1Ty &S1, const S2Ty &S2)

set_is_subset(A, B) - Return true iff A in B

void append_range(Container &C, Range &&R)

Wrapper function to append range R to container C.

LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI)

Create Printable object to print register units on a raw_ostream.

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

void sort(IteratorTy Start, IteratorTy End)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

auto instructionsWithoutDebug(IterT It, IterT End, bool SkipPseudoOp=true)

Construct a range iterator which begins at It and moves forwards until End is reached,...

LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

A special type used by analysis passes to provide an address that identifies that particular analysis...

Incoming for lane maks phi as machine instruction, incoming register Reg and incoming block Block are...

MachineBasicBlock * MBB

The basic block.

bool IsDone

True if the block that is ready for its final round of processing.

bool PrimaryPass

True if this is the first time we process the basic block.